公开(公告)号：US20240053892A1

公开(公告)日：2024-02-15

申请号：US18145552

申请日：2022-12-22

Applicant: Huazhong University Of Science And Technology ,  Zhejiang Lab

Inventor： Long ZHENG ,  Qinggang WANG ,  Xiaofei LIAO ,  Zhaozeng AN ,  Hai JIN

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0673 ,  G06F3/0656

Abstract: The present invention relates to a dynamic memory management apparatus and method for HLS, the apparatus at least comprising: several searching and caching modules and several modifying and writing-back modules, wherein the searching and caching modules are in connection with a DRAM storing module and a BRAM buffer, respectively, and the modifying and writing-back modules are in connection with the DRAM storing module and the BRAM buffer, respectively, wherein the BRAM buffer is for caching information about nodes on a search path and registering information about modification made to the nodes; the searching and caching module is for reading node data from the DRAM storing module according to received operators and node addresses, and writing the node data into the BRAM buffer; and the modifying and writing-back module reads the node data from the BRAM buffer and writes the node data back into the DRAM storing module. Aiming at the defect that the traditional operating system is directly transplanted to the FPGA and has low execution efficiency, the present invention utilizes the advantage of the large capacity of the DRAM on the FPGA to realize efficient dynamic memory allocation and deallocation, and improve the usability and code reusability of HLS.

公开(公告)号：US20240220541A1

公开(公告)日：2024-07-04

申请号：US18497233

申请日：2023-10-30

Applicant: Huazhong University of Science and Technology ,  Zhejiang Lab

Inventor： Long ZHENG ,  Chaoqiang LIU ,  Xiaofei LIAO ,  Hai JIN ,  Yu HUANG ,  Zhaozeng AN

IPC: G06F16/901

CPC classification number: G06F16/9024

Abstract: An FPGA-based method and system for accelerating graph construction is provided, the method including: sampling neighborhood of each vertex in stored data and recording a traversal order of the vertices; according to the vertex traversal order, grouping the vertices into blocks and processing them by block-granularity, so as to at least obtain distance values between each two sampled neighbors of vertices in each block; according to the said distance values, updating neighborhoods of the two relevant vertices; and processing all of the blocks, starting a new iteration, until a satisfying precision or a predetermined limit of the number of iterations has been reached. The present disclosure utilizes the advantages of FPGA platform including flexibility, low power consumption and high parallelism, combined with the characteristics of graph construction algorithm, thereby greatly improving construction speed and reducing processing power consumption, so as to enable large-scale graph construction task processing in the datacenter.