公开(公告)号：US07583772B2

公开(公告)日：2009-09-01

申请号：US11240678

申请日：2005-10-03

申请人： Hui Pan ,  Seong-Ho Lee ,  Michael Q. Le

发明人： Hui Pan ,  Seong-Ho Lee ,  Michael Q. Le

IPC分类号： H04L7/00

CPC分类号： G06F5/015 ,  G06F5/017 ,  G11C19/00

摘要： A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal.

摘要翻译： 使用一种系统和方法来允许产生相位旋转器控制信号，其中每个时钟周期使信号中的位数超过一个步长。 这可以通过以下操作完成。 存储包括多个数据位的第一和第二数据信号。 在每个时钟周期期间，基于相位控制信号来控制第一数据信号中的数据比特和随后的第二数据信号中的数据比特的旋转。 第一和第二受控数据信号被交织以形成第一和第二交错数据信号。 在时钟周期的后半段期间，基于相位控制信号的一部分来选择第一和第二交错数据信号中的一个。 最后，选择的数据信号作为相位控制信号发送。

公开(公告)号：US20090296868A1

公开(公告)日：2009-12-03

申请号：US12536186

申请日：2009-08-05

申请人： Hui PAN ,  Seong-Ho Lee ,  Michael Q. Le

发明人： Hui PAN ,  Seong-Ho Lee ,  Michael Q. Le

IPC分类号： H04L7/00

CPC分类号： G06F5/015 ,  G06F5/017 ,  G11C19/00

摘要： A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal.

摘要翻译： 使用一种系统和方法来允许产生相位旋转器控制信号，其中每个时钟周期使信号中的位数超过一个步长。 这可以通过以下操作完成。 存储包括多个数据位的第一和第二数据信号。 在每个时钟周期期间，基于相位控制信号来控制第一数据信号中的数据比特和随后的第二数据信号中的数据比特的旋转。 第一和第二受控数据信号被交织以形成第一和第二交错数据信号。 在时钟周期的后半段期间，基于相位控制信号的一部分来选择第一和第二交错数据信号中的一个。 最后，选择的数据信号作为相位控制信号发送。

公开(公告)号：US10951250B1

公开(公告)日：2021-03-16

申请号：US16855945

申请日：2020-04-22

申请人： Karim Vincent Abdelhalim ,  Michael Q. Le

发明人： Karim Vincent Abdelhalim ,  Michael Q. Le

IPC分类号： H04K1/02 ,  H04B1/04 ,  H04L25/03 ,  H03K5/003

摘要： A DC-shifting predriver has an input port configured for coupling to a serial data stream, an inverting output amplifier having an feedback node and an output port configured for coupling to a transistor at the input to a high-speed DAC or TX driver, and a capacitor AC-coupled between the input port and the feedback node. A weak feedback inverter having structure similar to, but less drive strength than the inverting output amplifier is coupled between the output port and the feedback node to act as a positive feedback latch. The predriver provides a DC shift up to 3V with high reliability and minimal intersymbol interference for data rates from 10 GS/s to 28 GS/s or higher. The predriver may provide multiple input ports implemented as a predriver array in an M-bit system, and the output amplifier may consist of N stages.

公开(公告)号：US07339478B2

公开(公告)日：2008-03-04

申请号：US11053311

申请日：2005-02-07

申请人： Michael Q. Le

发明人： Michael Q. Le

IPC分类号： G08B13/14

CPC分类号： G07C1/22 ,  G08G1/017 ,  G08G1/20

摘要： An apparatus and method for automatically tracking each individual vehicle, of a plurality of vehicles, in a race around a track. The device employs RFID tags on each of the vehicles being tracked. The device employs RFID tags and a gate to energize the tag to broadcast the vehicle's identity when a pass through the gate is determined. The device can be employed to both track the individual vehicle participants in a race, and to register the participants before the race. Races can be tracked on different courses in different geographic locations by placing the RFID tags on all participants and tracking their progress on the individual remote tracks from a central location.

摘要翻译： 一种用于在围绕轨道的赛道中自动跟踪多个车辆中的每个单独车辆的装置和方法。 该设备在被跟踪的每个车辆上使用RFID标签。 当确定通过门时，该装置使用RFID标签和门来激励标签以广播车辆的身份。 该装置可以用于在比赛中跟踪各车辆参与者，并在比赛前注册参赛者。 可以通过将RFID标签放置在所有参与者上，并从中心位置追踪他们在各个遥控轨道上的进度，从而在不同地理位置的不同课程上跟踪种族。

公开(公告)号：US10790636B1

公开(公告)日：2020-09-29

申请号：US16874464

申请日：2020-05-14

申请人： Karim Vincent Abdelhalim ,  Michael Q. Le

发明人： Karim Vincent Abdelhalim ,  Michael Q. Le

IPC分类号： H01S5/042 ,  H03K5/003 ,  H03M1/66

摘要： An H-bridge integrated laser driver optimizes power dissipation, impedance matching, low-swing and high-swing reliability for electro-absorption modulated laser (EML) and directly modulated laser diode (DML) applications. The laser driver includes a retimer for converting low-speed parallel data to a high-speed serial bit stream and to an inverted representation of the high-speed parallel bit stream, an M-bit PMOS DAC configured to receive a first buffered bit stream, an N-bit NMOS DAC configured to receive a second buffered bit stream substantially synchronized with the first buffered bit stream. A protective device is coupled between the M-bit DAC and the N-bit DAC. A first DC level-shifting predriver array is coupled between the retimer and the M-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream, and a second DC level-shifting predriver array is coupled between the retimer and the N-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream. An impedance matching module is coupled to an output of the protective device. The laser driver may be integrated on a CMOS communication chip.

公开(公告)号：US07706433B2

公开(公告)日：2010-04-27

申请号：US12320041

申请日：2009-01-15

申请人： Kevin T. Chan ,  Michael Q. Le

发明人： Kevin T. Chan ,  Michael Q. Le

IPC分类号： H04B1/38 ,  H03M9/00

CPC分类号： H04L12/40013 ,  H04J3/0685 ,  H04L12/28 ,  H04L12/4625 ,  H04L43/00

摘要： A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

摘要翻译： 物理层设备（PLD）包括第一串行器 - 解串器（SERDES）设备和第二SERDES设备。 每个SERDES设备包括具有被配置为与各种网络设备通信串行数据的串行端口的模拟部分，以及被配置为与其他各种网络设备通信并行数据的数字部分。 PLD包括第一信号路径，其被配置为在SERDES设备的模拟部分之间路由串行数据信号，绕过SERDES设备的数字部分。 因此，SERDES设备可以直接通信串行数据，而无需执行并行数据转换。 第二信号路径被配置为在SERDES设备的模拟部分之间路由恢复的时钟和数据信号，但仍然绕过SERDES设备的数字部分。 恢复的时钟和数据信号在通过网络设备发送之前被重新生成。

公开(公告)号：US07486721B2

公开(公告)日：2009-02-03

申请号：US11892290

申请日：2007-08-21

申请人： Kevin T. Chan ,  Michael Q. Le

发明人： Kevin T. Chan ,  Michael Q. Le

IPC分类号： H04B1/38 ,  H03M9/00

CPC分类号： H04L12/40013 ,  H04J3/0685 ,  H04L12/28 ,  H04L12/4625 ,  H04L43/00

摘要： A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

摘要翻译： 物理层设备（PLD）包括第一串行器 - 解串器（SERDES）设备和第二SERDES设备。 每个SERDES设备包括具有被配置为与各种网络设备通信串行数据的串行端口的模拟部分，以及被配置为与其他各种网络设备通信并行数据的数字部分。 PLD包括第一信号路径，其被配置为在SERDES设备的模拟部分之间路由串行数据信号，绕过SERDES设备的数字部分。 因此，SERDES设备可以直接通信串行数据，而无需执行并行数据转换。 第二信号路径被配置为在SERDES设备的模拟部分之间路由恢复的时钟和数据信号，但仍然绕过SERDES设备的数字部分。 恢复的时钟和数据信号在通过网络设备发送之前被重新生成。

公开(公告)号：US08233578B2

公开(公告)日：2012-07-31

申请号：US11649809

申请日：2007-01-05

申请人： Chun-Ying Chen ,  Michael Q. Le ,  Myles Wakayama

发明人： Chun-Ying Chen ,  Michael Q. Le ,  Myles Wakayama

IPC分类号： H03D3/24

CPC分类号： H03L7/0998 ,  G11B20/1403 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/0996 ,  H03L7/18 ,  H04L7/0025 ,  H04L7/033

摘要： A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the PLL. The PLL includes a phase detector, a low pass filter, a charge pump, a voltage controlled oscillator (“VCO”), and a feedback path connecting output of the VCO to the phase detector. The feedback path includes a phase rotator connected to the output of the VCO and to an input of a frequency divider. Coarse frequency control is implemented by adjusting the input reference frequency to the phase detector or by adjusting the divider ratio of the frequency divider. Fine frequency control is achieved by increasing or decreasing the rotation speed of the phase rotator. The phase rotator constantly rotates phase of the VCO output, thereby causing a frequency shift at the output of the phase rotator.

摘要翻译： 锁相环频率合成器包括在PLL的反馈路径中的相位旋转器。 PLL包括相位检测器，低通滤波器，电荷泵，压控振荡器（“VCO”）以及将VCO的输出连接到相位检测器的反馈路径。 反馈路径包括连接到VCO的输出端和分频器的输入端的相位旋转器。 通过调整相位检测器的输入参考频率或调整分频器的分频比来实现粗频率控制。 通过增加或减小相位旋转器的转速来实现精细的频率控制。 相位旋转器不断地转动VCO输出的相位，从而在相位旋转器的输出处引起频率偏移。

公开(公告)号：US07848394B2

公开(公告)日：2010-12-07

申请号：US11013790

申请日：2004-12-17

申请人： Raymond L. Clancy ,  Michael Q. Le

发明人： Raymond L. Clancy ,  Michael Q. Le

IPC分类号： H04B1/38

CPC分类号： H03M9/00 ,  H04J3/0685 ,  H04L7/0012

摘要： A first serial transceiver has a reference clock, a first transmitter, and a first receiver. The first receiver includes (i) a phase detector, and (ii) a phase rotator. The phase rotator is driven by the reference clock. A first multiplexer is coupled to the first receiver. The first multiplexer receives the phase detector output and a control signal. When the first serial transceiver is in a test configuration, the first multiplexer passes the control signal to the phase rotator, thereby varying the frequency of the phase rotator output. A second multiplexer is coupled to the first transmitter. The second multiplexer receives a reference clock signal and the phase rotator output. When the first serial transceiver is in a test configuration, the second multiplexer passes the phase rotator output to the first transmitter. The first transmitter thereby transmits a serial data stream that varies in frequency from said reference clock.

摘要翻译： 第一串行收发器具有参考时钟，第一发射器和第一接收器。 第一接收机包括（i）相位检测器和（ii）相位旋转器。 相位旋转器由参考时钟驱动。 第一多路复用器耦合到第一接收机。 第一多路复用器接收相位检测器输出和控制信号。 当第一串行收发器处于测试配置时，第一多路复用器将控制信号传递到相位旋转器，从而改变相位旋转器输出的频率。 第二多路复用器耦合到第一发射机。 第二多路复用器接收参考时钟信号和相位旋转器输出。 当第一串行收发器处于测试配置中时，第二复用器将相位旋转器输出传递到第一发射机。 因此，第一发射机从而发射频率与所述参考时钟变化的串行数据流。

公开(公告)号：US11216024B1

公开(公告)日：2022-01-04

申请号：US17207669

申请日：2021-03-20

申请人： Mrunmay Talegaonkar ,  Michael Q. Le

发明人： Mrunmay Talegaonkar ,  Michael Q. Le

IPC分类号： G06F1/08 ,  G06F1/10

摘要： A referenceless frequency acquisition scheme locks to an unknown data frequency by feedback of sampled data to a digitally controlled oscillator (DCO). A received data signal is converted to deserialized outputs, then by a phase detector to symbol streams of phase updates. Each symbol stream is converted to a lower rate sum, for which absolute values are computed and periodically summed. Absolute value sums are obtained for each frequency over a range of test frequencies to obtain totals, each corresponding to a different test frequency. A critical value is determined from among the totals. The DCO is set to the test frequency corresponding to the critical value as a coarse approximation for the unknown frequency. In subsequent iterations, proportional feedback to the DCO of lower rate sums of symbol streams is combined with integral feedback of codes representing finer approximations of the unknown data frequency swept over successively narrowing bands, and the DCO is locked to the finest approximation that lies between consecutive codes corresponding to sums having opposite signs.