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    Cross-checking for on-the-fly Reed Solomon error correction code
    1.
    发明授权
    Cross-checking for on-the-fly Reed Solomon error correction code 失效
    交叉检查即时Reed Solomon纠错码

    公开(公告)号：US5422895A

    公开(公告)日：1995-06-06

    申请号：US820283

    申请日：1992-01-09

    申请人： Hung C. Nguyen ,  Thomas D. Howell ,  Bruce R. Peterson

    发明人： Hung C. Nguyen ,  Thomas D. Howell ,  Bruce R. Peterson

    IPC分类号： H03M13/01 ,  H03M13/15 ,  G06F11/10 ,  H03M13/00

    CPC分类号： H03M13/01 ,  H03M13/151

    摘要： An improved cross-checking circuit is provided for use within a Reed-Solomon error correction and cross checking apparatus for performing error correction and cross checking upon a data block within an incoming stream of substantially contiguous data blocks flowing from a source to a destination. The circuit is based upon a distinguished primitive element, alpha.sup.1 (2B (Hex))=x.sup.5 +x.sup.3 +x+1, of a Galois field whose elements are represented by residue classes of binary polynomials modulo p(x)=x.sup.8 +x.sup.4 +x.sup.3 +x.sup.2 +1. The apparatus includes a microcontroller for supervising the flow of the data blocks and for making calculations related to error corrections, and a Galois field syndrome generator and remainder recovery circuit is connected to receive the incoming stream and recover therefrom plural error correction remainder bytes for each block and selectively to hold said bytes in a syndrome latch, the remainder bytes being related to syndrome bytes appended to the data block. The generator and remainder recovery circuit includes the Reed-Solomon cross-checking circuit for recovering cross-checking remainder information related to cross check syndrome information in accordance with the polynomial GXC(x)=x.sup.2 +alpha.sup. 134 x+alpha.sup.1.

    摘要翻译： 提供了一种改进的交叉检查电路，用于在Reed-Solomon纠错和交叉检查装置中使用，用于对从源到目的地流动的基本相邻的数据块的输入流中的数据块执行纠错和交叉检查。 该电路基于伽罗瓦域的识别原始元素α1（2B（Hex））= x5 + x3 + x + 1，其元素由模p（x）= x8 + x4 +的二进制多项式的残差类别表示， x3 + x2 + 1。 该装置包括用于监视数据块的流动并进行与误差校正相关的计算的微控制器，并且伽罗瓦域校正子发生器和余数恢复电路被连接以接收输入流并从其中恢复每个块的多个纠错余数字节 并且选择性地将所述字节保持在校正子锁存器中，其余字节与附加到数据块的校验码字节相关。 发生器和余数恢复电路包括Reed-Solomon交叉检查电路，用于根据多项式GXC（x）= x2 +α1×134x +α1来恢复与交叉检验校正子信息相关的交叉检验余数信息。

    Method and apparatus for asymmetrical RLL coding
    3.
    发明授权
    Method and apparatus for asymmetrical RLL coding 失效
    用于不对称RLL编码的方法和装置

    公开(公告)号：US4949196A

    公开(公告)日：1990-08-14

    申请号：US175171

    申请日：1988-03-30

    申请人： Neil R. Davie ,  Martin A. Hassner ,  Thomas D. Howell ,  Razmik Karabed ,  Paul H. Siegel

    发明人： Neil R. Davie ,  Martin A. Hassner ,  Thomas D. Howell ,  Razmik Karabed ,  Paul H. Siegel

    IPC分类号： H03M7/14 ,  G06T9/00 ,  G11B20/14 ,  H03M5/14

    CPC分类号： H03M5/145 ,  G06T9/005

    摘要： This disclosure concerns for generating asymmetrically constrained run-length-limited encoded data from a serialized binary string of 1's and 0's. The method comprises the steps of encoding the input data bits using a run-length-limited constraint in the form of M/N (d,k), where M is the number of input data bits, N is the number of output bits associated therewith, d is the minimum number of 0 data bits between adjacent data bit 1's, and k is the maximum number of 0 data bits between adjacent 1's; and alternating the values of d and k between a set (d.sub.1, k.sub.1) and a set (d.sub.2, k.sub.2), respectively, where d.sub.1 .noteq.d.sub.2. The apparatus comprises means for generating N output data bits in response to M input data bits and for generating data bit 0's between data bit 1's based upon a run-length-limited coding constraints (d.sub.1, k.sub.1) and (d.sub.2, k.sub.2), where constraints (d.sub.1, k.sub.1) and (d.sub.2, k.sub.2) apply alternately to runs of zeroes between output data ones. Fractional numerical values of d.sub.1 and d.sub.2 can be employed in the method or apparatus.

    摘要翻译： 本公开涉及从1和0的串行化二进制串生成不对称约束的游程长度限制编码数据。 该方法包括以M / N（d，k）形式的游程限制约束对输入数据比特进行编码的步骤，其中M是输入数据比特数，N是相关联的输出比特数 因此，d是相邻数据位1之间的0个数据位的最小数量，k是相邻1之间的0个数据位的最大数量; 并且分别在集合（d1，k1）和集合（d2，k2）之间交替d和k的值，其中d1 NOTEQUAL d2。 该装置包括用于响应于M个输入数据位产生N个输出数据位并用于基于游程长度限制编码约束（d1，k1）和（d2，k2）在数据位1之间产生数据位0的装置，其中 约束（d1，k1）和（d2，k2）交替应用于输出数据之间的零运行。 d1和d2的分数值可以在该方法或装置中使用。