公开(公告)号：US06828217B2

公开(公告)日：2004-12-07

申请号：US10284707

申请日：2002-10-31

申请人： Hung C. Nguyen ,  I-Ching T. Yang

发明人： Hung C. Nguyen ,  I-Ching T. Yang

IPC分类号： H01L21301

CPC分类号： H01L21/6835 ,  H01L21/0273 ,  H01L21/304 ,  H01L21/3086 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834

摘要： A semiconductor wafer and a method for fabricating a semiconductor wafer having improved dicing lanes are provided. The dicing lanes include grooves formed by photolithography and etching processes. The wafer also includes a plating layer on a back side of the wafer to facilitate bonding of individual circuit chips to a suitable substrate and to effect efficient heat transfer between the chip and the substrate. Photolithography and etching processes are employed to etch horizontal and vertical lanes in the plating layer to facilitate breaking of the individual chips from the wafer. The horizontal and vertical lanes etched in the plating layer are coincident to the grooves etched in the substrate. The wafer can then be broken into individual circuit chips by applying stress to the back of the wafer, such that the wafer cleanly breaks along the horizontal and vertical dicing lanes and the etched grooves.

摘要翻译： 提供半导体晶片和制造具有改进的切割通道的半导体晶片的方法。 切割车道包括通过光刻和蚀刻工艺形成的凹槽。 晶片还包括在晶片的背面上的镀层，以便于将各个电路芯片接合到合适的衬底并且实现芯片和衬底之间的有效的热传递。 采用光刻和蚀刻工艺来蚀刻镀层中的水平和垂直通道以便于从晶片破碎各个芯片。 在镀层中蚀刻的水平和垂直通道与在衬底中蚀刻的槽重合。 然后通过向晶片的背面施加应力，将晶片分解为单独的电路芯片，使得晶片沿着水平和垂直切割通道和蚀刻的沟槽干净地断裂。

公开(公告)号：US5572244A

公开(公告)日：1996-11-05

申请号：US280973

申请日：1994-07-27

申请人： Donald J. Drake ,  Hung C. Nguyen

发明人： Donald J. Drake ,  Hung C. Nguyen

IPC分类号： B41J2/155 ,  B41J2/16 ,  G01D15/18 ,  B41J2/14

CPC分类号： B41J2/1635 ,  B41J2/155 ,  B41J2/1604 ,  B41J2/1623 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2202/20 ,  B41J2202/21 ,  Y10T29/49083 ,  Y10T29/49401

摘要： A large array or pagewidth printhead fabricated from printhead elements or subunits having adhesive-free butting edges. Each of the printhead elements includes a heater element and a channel element bonded together by an adhesive such as an epoxy. A space or adhesive-receiving aperture is formed between the channel element and the heater element before mating so that any adhesive forced from between the channel element and heater element by the pressure of mating does not flow onto the butting surfaces, but instead overflows into the space thereby maintaining an adhesive free butting edge. The channel element includes an etch trough which forms the space. The printhead elements are butted together to form a large array printhead. The absence of adhesive on the butting edges improves manufacturability of the large array printhead.

摘要翻译： 由打印头元件或具有无粘合剂对接边缘的子单元制造的大阵列或页宽打印头。 每个打印头元件包括加热器元件和通过诸如环氧树脂的粘合剂粘合在一起的通道元件。 在配合之前，在通道元件和加热器元件之间形成空间或粘合剂接收孔，使得通过配合压力从通道元件和加热器元件之间强制的任何粘合剂不会流到对接表面上，而是溢流到 空间，从而保持无粘合剂的对接边缘。 通道元件包括形成空间的蚀刻槽。 打印头元件对接在一起以形成大阵列打印头。 对接边缘上没有粘合剂提高了大阵列打印头的可制造性。

公开(公告)号：US5422760A

公开(公告)日：1995-06-06

申请号：US291957

申请日：1994-08-17

申请人： William L. Abbott ,  Hung C. Nguyen ,  Kenneth E. Johnson

发明人： William L. Abbott ,  Hung C. Nguyen ,  Kenneth E. Johnson

IPC分类号： G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  H03M13/23 ,  H04L25/49 ,  G11B5/09 ,  G11B5/035 ,  G11B27/10

CPC分类号： G11B20/10 ,  H04L25/4908 ,  G11B20/1258

摘要： A class IV partial response, maximum likelihood data channel for a disk drive includes an encoder connected to a data sequencer for converting user data blocks into a predetermined 8/9ths code such as a (0,4,4,) code. A precoder conveys the 8/9ths code into class IV code. An analog write driver supplies the class IV code to a data transducer head during data write-to-disk operations. A read channel connected to the head amplifies and conditions analog signals during data read operations. A quantizer produces samples of the analog signals in accordance with a quantization clock generated by a clock generator. An adaptive FIR filter means is conditions the data samples in accordance with selectable, adaptive filter coefficients. A Viterbi detector puts out the class IV code from the filtered and quantized samples. A postcoder conveys the detected class IV code into detected 8/9ths code. A decoder converts the detected 8/9ths code into user data and supplies user data to the sequencer. The programmable FIR filter is provided with servo coefficients during reading of the servo sectors, and an asynchronous servo detector detects head position information from the quantized and filtered samples without phase locking of the quantization clock generator to the quantized servo samples. The asynchronous servo detector is also used to aid detection of sync field preamble information before the FIR filter is fully adapted. Multi-mode gain and timing loops are also a part of the present invention.

摘要翻译： 用于磁盘驱动器的IV类部分响应，最大似然数据通道包括连接到数据定序器的编码器，用于将用户数据块转换成诸如（0,4,4）代码的预定的8/9代码。 预编码器将8/9代码传送到IV类代码。 模拟写入驱动器在数据写入到磁盘操作期间将IV类代码提供给数据传感器头。 连接到头的读通道在数据读取操作期间放大和调节模拟信号。 量化器根据由时钟发生器产生的量化时钟产生模拟信号的样本。 自适应FIR滤波器装置根据可选择的自适应滤波器系数来调节数据样本。 维特比检测器从滤波和量化样本中提取出IV类码。 后检测器将检测到的IV类代码传送到检测到的8/9代码。 解码器将检测到的8/9代码转换成用户数据，并将用户数据提供给定序器。 可编程FIR滤波器在读取伺服扇区期间提供伺服系数，并且异步伺服检测器从量化和滤波的采样中检测头位置信息，而不将量化时钟发生器锁定到量化的伺服采样。 异步伺服检测器还用于在FIR滤波器完全适配之前辅助检测同步字段前导码信息。 多模式增益和定时回路也是本发明的一部分。

公开(公告)号：US5381359A

公开(公告)日：1995-01-10

申请号：US936761

申请日：1992-08-27

申请人： William L. Abbott ,  Hung C. Nguyen

发明人： William L. Abbott ,  Hung C. Nguyen

IPC分类号： G11B20/10 ,  G11B20/12 ,  H04L25/49 ,  G06F7/38 ,  H03H7/30

CPC分类号： G11B20/10 ,  H04L25/4908 ,  G11B20/1258

摘要： A digital adaptive finite impulse response filter circuit is provided for a PR4,ML sampled data channel including an analog to digital sampler for providing raw digital samples of data to the filter circuit and a sampled data detector for detecting coded data from conditioned digital samples received from the filter circuit. The filter circuit comprises a multi-tap transversal filter structure wherein each tap is connected to receive a selected coefficient, a source of a plurality of coefficients for each tap, a coefficient selector connected to the source to receive the plurality of coefficients and to provide a selected coefficient to each tap of the transversal filter structure, and a control circuit for controlling the coefficient selector and the source for providing each of the selected coefficients to a corresponding tap of the transversal filter structure. Training and adaptation methods and circuits for adapting the filter structure are also described.

摘要翻译： 为包括模拟数字采样器的PR4，ML采样数据通道提供数字自适应有限脉冲响应滤波器电路，用于向滤波电路提供数据的原始数字采样，以及采样数据检测器，用于检测从 滤波电路。 滤波器电路包括多抽头横向滤波器结构，其中每个抽头被连接以接收所选择的系数，用于每个抽头的多个系数的源;连接到源以接收多个系数的系数选择器， 选择的系数到横向滤波器结构的每个抽头，以及控制电路，用于控制系数选择器和源，以将每个所选择的系数提供给横向滤波器结构的对应抽头。 还描述了用于适配滤波器结构的训练和适应方法和电路。

公开(公告)号：US5341387A

公开(公告)日：1994-08-23

申请号：US936759

申请日：1992-08-27

申请人： Hung C. Nguyen

发明人： Hung C. Nguyen

IPC分类号： G11B20/10 ,  G11B20/12 ,  H04L25/49 ,  H04L1/00 ,  G06J1/00

CPC分类号： H04L25/4908 ,  G11B20/10 ,  G11B20/1258

摘要： A Viterbi detector for a PR4,ML data channel includes a data sample input for receiving digital data samples from a source. Digital data samples are taken of data which has been coded in a predetermined data code format and which has been passed through a data degrading channel. A delay circuit delays the digital data samples received at the data sample input. A delay selector controls an output of the delay circuit in accordance with a feedback control bit value. An adder circuit combines data samples from the data sample input with delayed samples from the delay circuit to produce a sum. A threshold input receives programmable positive and negative data threshold values. A threshold selector puts out either the positive or the negative threshold values in accordance with a sign bit control value. A comparator compares the sum with a selected threshold value and puts out a logical value based upon comparison thereof. It includes Viterbi decision state logic for determining the sign bit control value, the feedback control bit value, and two raw data bits for each incoming data sample. A memory path circuit decodes a sequence of consecutive values of the raw data bits in accordance with a predetermined maximum likelihood trellis decode logic table related to the predetermined data code format and puts out a sequence of detected code bits.

摘要翻译： 用于PR4，ML数据通道的维特比检测器包括用于从源接收数字数据采样的数据采样输入。 数据数据样本取已经以预定数据码格式编码并已经通过数据降级信道的数据。 延迟电路延迟在数据采样输入端接收的数字数据样本。 延迟选择器根据反馈控制位值控制延迟电路的输出。 加法器电路将来自数据采样输入的数据采样与来自延迟电路的延迟采样相结合，产生和。 阈值输入接收可编程的正和负数据阈值。 阈值选择器根据符号位控制值输出正阈值或负阈值。 比较器将和与选择的阈值进行比较，并根据其比较输出逻辑值。 它包括用于确定每个输入数据样本的符号位控制值，反馈控制位值和两个原始数据位的维特比判决状态逻辑。 存储器路径电路根据与预定数据代码格式相关的预定最大似然网格解码逻辑表来解码原始数据位的连续值序列，并且输出检测到的代码位序列。

公开(公告)号：US5341249A

公开(公告)日：1994-08-23

申请号：US937064

申请日：1992-08-27

申请人： William L. Abbott ,  Hung C. Nguyen ,  Kenneth E. Johnson

发明人： William L. Abbott ,  Hung C. Nguyen ,  Kenneth E. Johnson

IPC分类号： G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  H03M13/23 ,  H04L25/49 ,  G11B5/09

CPC分类号： G11B20/10 ,  H04L25/4908 ,  G11B20/1258

摘要： A class IV partial response, maximum likelihood data channel for a disk drive includes an encoder connected to a data sequencer for converting user data blocks into a predetermined 8/9ths code such as a (0,4,4,) code. A precoder converts the 8/9ths code into class IV code. An analog write driver supplies the class IV code to a data transducer head during data write-to-disk operations. A read channel connected to the head amplifies and conditions analog signals during data read operations. A quantizer produces samples of the analog signals in accordance with a quantization clock generated by a clock generator. An adaptive FIR filter means is conditions the data samples in accordance with selectable, adaptive filter coefficients. A Viterbi detector puts out the class IV code from the filtered and quantized samples. A postcoder converts the detected class IV code into detected 8/9ths code. A decoder converts the detected 8/9ths code into user data and supplies user data to the sequencer. The programmable FIR filter is provided with servo coefficients during reading of the servo sectors, and an asynchronous servo detector detects head position information from the quantized and filtered samples without phase locking of the quantization clock generator to the quantized servo samples. The asynchronous servo detector is also used to aid detection of sync field preamble information before the FIR filter is fully adapted. Multi-mode gain and timing loops are also a part of the present invention.

摘要翻译： 用于磁盘驱动器的IV类部分响应，最大似然数据通道包括连接到数据定序器的编码器，用于将用户数据块转换成诸如（0,4,4）代码的预定的8/9代码。 预编码器将8/9代码转换为IV类代码。 模拟写入驱动器在数据写入到磁盘操作期间将IV类代码提供给数据传感器头。 连接到头的读通道在数据读取操作期间放大和调节模拟信号。 量化器根据由时钟发生器产生的量化时钟产生模拟信号的样本。 自适应FIR滤波器装置根据可选择的自适应滤波器系数来调节数据样本。 维特比检测器从滤波和量化的样本中输出IV类码。 后检测器将检测到的IV类代码转换为检测到的8/9代码。 解码器将检测到的8/9代码转换成用户数据，并将用户数据提供给定序器。 可编程FIR滤波器在读取伺服扇区期间提供伺服系数，并且异步伺服检测器从量化和滤波的采样中检测头位置信息，而不将量化时钟发生器锁定到量化的伺服采样。 异步伺服检测器还用于在FIR滤波器完全适配之前辅助检测同步字段前导码信息。 多模式增益和定时回路也是本发明的一部分。

公开(公告)号：US07986736B2

公开(公告)日：2011-07-26

申请号：US11467914

申请日：2006-08-28

申请人： Hung C. Nguyen ,  Catherine A. French ,  Jayesh Desai ,  Ruoyang Lu ,  Ali D. Pirooz

发明人： Hung C. Nguyen ,  Catherine A. French ,  Jayesh Desai ,  Ruoyang Lu ,  Ali D. Pirooz

IPC分类号： H04K1/10

CPC分类号： H04L1/0072 ,  H04B1/71637 ,  H04B1/7183 ,  H04L5/023 ,  H04L27/2656 ,  H04L27/2657 ,  H04L27/2662

摘要： An ultra wideband receiver, based on multiband orthogonal frequency division multiplexing (MB-OFDM), combines digital data from multiple channels after signal processing and before decoding. The receiver provides a master controller that synthesizes packet synchronization, frame synchronization, and sampling frequency offset information from multiple channels into signals that simultaneously control all channels of the receiver.

摘要翻译： 基于多频带正交频分复用（MB-OFDM）的超宽带接收机在信号处理和解码之前组合来自多个信道的数字数据。 接收机提供一个主控制器，它将分组同步，帧同步和从多个信道的采样频率偏移信息合成到同时控制接收机的所有信道的信号中。

公开(公告)号：US5661760A

公开(公告)日：1997-08-26

申请号：US686998

申请日：1996-07-24

申请人： Ara Patapoutian ,  Matthew P. Vea ,  Hung C. Nguyen

发明人： Ara Patapoutian ,  Matthew P. Vea ,  Hung C. Nguyen

IPC分类号： G11B5/55 ,  G11B5/596 ,  G11B20/10 ,  G11B20/18 ,  G11B21/10 ,  G11B27/30 ,  H03M13/23 ,  H04L25/49 ,  H04D27/06 ,  H03D1/00

CPC分类号： H04L25/4904 ,  G11B20/10009 ,  G11B27/3027 ,  G11B5/5526 ,  G11B5/59688 ,  G11B2220/20 ,  G11B5/5965

摘要： A synchronous sampling data detection channel includes a data transducer head positioned by a servo-controlled actuator over a recording track of a rotating data storage disk, a preamplifier for receiving electrical analog signals magnetically induced by the data transducer head from flux transitions present in at least the servo information field, a digital sampler for synchronously sampling the electrical analog signals to produce digital samples, and a Viterbi detector coupled to receive digital samples from the synchronous sampling data detection channel for decoding 1/4 T coded wide biphase servo information patterns patterns as maximum likelihood servo data sequences, wherein the wide biphase magnet patterns are arranged e.g. as ++-- magnet patterns for a binary zero information value and --++ magnet patterns for a binary one information value.

摘要翻译： 同步采样数据检测通道包括由伺服控制致动器定位在旋转数据存储盘的记录轨道上的数据传感器头，前置放大器，用于接收至少由数据传感器头磁场感应的电流模拟信号 伺服信息字段，用于同步采样电气模拟信号以产生数字样本的数字采样器，以及耦合以从同步采样数据检测通道接收数字采样的维特比检测器，用于将1/4 T编码的宽双相伺服信息模式图案解码为 最大似然伺服数据序列，其中布置宽双相磁体图案例如 作为二进制零信息值的++ - 磁体模式和二进制一个信息值的++磁体模式。

公开(公告)号：US5345342A

公开(公告)日：1994-09-06

申请号：US192146

申请日：1994-02-04

申请人： William L. Abbott ,  Hung C. Nguyen ,  Kenneth E. Johnson

发明人： William L. Abbott ,  Hung C. Nguyen ,  Kenneth E. Johnson

IPC分类号： G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  H03M13/23 ,  H04L25/49 ,  G11B5/09 ,  G11B5/596

CPC分类号： G11B20/10 ,  H04L25/4908 ,  G11B20/1258

摘要： A class IV partial response, maximum likelihood data channel for a disk drive includes an encoder connected to a data sequencer for converting user data blocks into a predetermined 8/9ths code such as a (0,4,4,) code. A precoder converts the 8/9ths code into class IV code. An analog write driver supplies the class IV code to a data transducer head during data write-to-disk operations. A read channel connected to the head amplifies and conditions analog signals during data read operations. A quantizer produces samples of the analog signals in accordance with a quantization clock generated by a clock generator. An adaptive FIR filter means is conditions the data samples in accordance with selectable, adaptive filter coefficients. A Viterbi detector puts out the class IV code from the filtered and quantized samples. A postcoder converts the detected class IV code into detected 8/9ths code. A decoder converts the detected 8/9ths code into user data and supplies user data to the sequencer. The programmable FIR filter is provided with servo coefficients during reading of the servo sectors, and an asynchronous servo detector detects head position information from the quantized and filtered samples without phase locking of the quantization clock generator to the quantized servo samples. The asynchronous servo detector is also used to aid detection of sync field preamble information before the FIR filter is fully adapted. Multi-mode gain and timing loops are also a part of the present invention.

摘要翻译： 用于磁盘驱动器的IV类部分响应，最大似然数据通道包括连接到数据定序器的编码器，用于将用户数据块转换成诸如（0,4,4）代码的预定的8/9代码。 预编码器将8/9代码转换为IV类代码。 模拟写入驱动器在数据写入到磁盘操作期间将IV类代码提供给数据传感器头。 连接到头的读通道在数据读取操作期间放大和调节模拟信号。 量化器根据由时钟发生器产生的量化时钟产生模拟信号的样本。 自适应FIR滤波器装置根据可选择的自适应滤波器系数来调节数据样本。 维特比检测器从滤波和量化的样本中输出IV类码。 后检测器将检测到的IV类代码转换为检测到的8/9代码。 解码器将检测到的8/9代码转换成用户数据，并将用户数据提供给定序器。 可编程FIR滤波器在读取伺服扇区期间提供伺服系数，并且异步伺服检测器从量化和滤波的采样中检测头位置信息，而不将量化时钟发生器锁定到量化的伺服采样。 异步伺服检测器还用于在FIR滤波器完全适配之前辅助检测同步字段前导码信息。 多模式增益和定时回路也是本发明的一部分。

公开(公告)号：US5321559A

公开(公告)日：1994-06-14

申请号：US937352

申请日：1992-08-27

申请人： Hung C. Nguyen ,  William L. Abbott

发明人： Hung C. Nguyen ,  William L. Abbott

IPC分类号： G11B5/012 ,  G11B20/10 ,  G11B20/12 ,  H04L25/49 ,  G11B5/09 ,  G11B5/035

CPC分类号： G11B20/10 ,  H04L25/4908 ,  G11B20/1258 ,  G11B5/012

摘要： A digital peak detection circuit asynchronously detects embedded overhead information such as servo or sync pattern data within a PR4,ML synchronous data detection channel of a magnetic disk drive. The channel includes an analog to digital converter clocked by a data clock operating asynchronously with respect to playback of the embedded overhead information in the channel for converting an analog data stream into raw data samples, and an adaptive digital FIR filter for conditioning the raw data samples into conditioned data samples in accordance with programmable filter coefficients. The digital peak detection circuit includes a filter adaptation circuit for programming the digital FIR filter to a bandwidth characteristic selected for the embedded overhead information, a plurality of tapped clock delays each connected in tandem to receive and progressively by a period related to said data clock to delay conditioned data samples of the embedded overhead information, a first comparison logic array connected to predetermined taps of said tapped data clock period delays for comparing said conditioned data samples of the embedded overhead information at said taps and for generating a first logical condition therefrom, a second comparison logic array connected to a predetermined tap of said tapped clock delay means and to a threshold-providing circuit, for comparing the conditioned data samples of the embedded overhead information at the taps with threshold values provided by the threshold-providing circuit and for generating a second logical condition therefrom, and a digital combining circuit for combining the first logical condition and the second logical condition in order to detect and put out the embedded overhead information. A fault tolerant sync pattern detection method and apparatus is also disclosed.

摘要翻译： 数字峰值检测电路在磁盘驱动器的PR4，ML同步数据检测通道内异步检测嵌入式开销信息，例如伺服或同步模式数据。 该通道包括一个模数转换器，由数据时钟异步运行，数据时钟相对于用于将模拟数据流转换为原始数据样本的通道中的嵌入式开销信息的重放，以及用于调节原始数据样本的自适应数字FIR滤波器 根据可编程滤波器系数到条件数据样本。 数字峰值检测电路包括滤波器适配电路，用于将数字FIR滤波器编程为针对嵌入式开销信息选择的带宽特性，多个抽头时钟延迟，每个抽头时钟延迟串联连接以逐渐接收与所述数据时钟相关的周期 延迟所述嵌入式开销信息的经调节的数据样本，连接到所述抽头数据时钟周期延迟的预定抽头的第一比较逻辑阵列，用于比较所述抽头处的嵌入开销信息的所述经调节的数据样本，并用于从其产生第一逻辑条件; 连接到所述抽头时钟延迟装置的预定抽头的第二比较逻辑阵列和阈值提供电路，用于将抽头处的嵌入开销信息的条件数据样本与由阈值提供电路提供的阈值进行比较， 第二个逻辑条件，和ad 用于组合第一逻辑条件和第二逻辑条件的数字组合电路，以便检测和推出嵌入式开销信息。 还公开了容错同步模式检测方法和装置。