公开(公告)号：US20130055177A1

公开(公告)日：2013-02-28

申请号：US13596069

申请日：2012-08-28

申请人： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

发明人： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F2217/14

摘要： User's RTL design is analyzed and instrumented so that signals of interest are preserved and can be located in the net list after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the net list to ensure that signal values can be accessed at runtime. After that, a P&R process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in FPGAs. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

摘要翻译： 对用户的RTL设计进行分析和检测，以便保留感兴趣的信号，并在合成后将其置于网络列表中。 然后，执行用户的RTL合成和设计分区的原始流程。 分析输出以定位感兴趣的信号。 锁存器有选择地插入到网络列表中，以确保在运行时可以访问信号值。 之后，执行P＆R处理，并分析输出以将信号名称与FPGA中的寄存器（触发器和锁存器）或存储器块位置相关联。 建立并保存关联数据库以供运行时使用。 在运行期间，可以在工作站上提供软件组件，供用户查询与RTL分层信号名称对应的信号值。

公开(公告)号：US08739089B2

公开(公告)日：2014-05-27

申请号：US13596069

申请日：2012-08-28

申请人： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

发明人： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F7/62

CPC分类号： G06F17/5054 ,  G06F2217/14

摘要： User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

摘要翻译： 用户的寄存器传输级别（RTL）设计进行分析和检测，以使感兴趣的信号得以保留，并且可以在合成后位于网表中。 然后，执行用户的RTL合成和设计分区的原始流程。 分析输出以定位感兴趣的信号。 锁存器有选择地插入到网表中，以确保在运行时可以访问信号值。 之后，执行位置和路由（P＆R）处理，并分析输出以将信号名称与现场可编程门阵列（FPGA）器件中的寄存器（触发器和锁存器）或存储器块位置相关联。 建立并保存关联数据库以供运行时使用。 在运行期间，可以在工作站上提供软件组件，供用户查询与RTL分层信号名称对应的信号值。

公开(公告)号：US20130035925A1

公开(公告)日：2013-02-07

申请号：US13597997

申请日：2012-08-29

申请人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

发明人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

IPC分类号： G06F9/455

CPC分类号： G06F17/5027

摘要： A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation.

摘要翻译： 用于模拟电路设计的方法包括在仿真界面处接收与来自定制原型板的验证模块相关联的信号值，其可以由至少一个电路板描述文件描述，并且可以包括至少一个现场可编程门 阵列仿真电路设计。 所述方法还可以包括处理，所探测的信号值与被仿真的电路设计的一部分相关联，所述仿真接口能够被配置为向至少所述验证模块提供定时和控制信息，并且可以包括控制器和 存储器件，其中控制器能够被配置为接收探测信号值。 该方法还可以包括存储处理后的信息并将其发送到主机工作站。

公开(公告)号：US08732650B2

公开(公告)日：2014-05-20

申请号：US13597997

申请日：2012-08-29

申请人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

发明人： Yingtsai Chang ,  Sweyyan Shei ,  Hung Chun Chiu ,  Hwa Mao ,  Ming Yang Wang ,  Yuchin Hsu

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation.

摘要翻译： 用于模拟电路设计的方法包括在仿真界面处接收与来自定制原型板的验证模块相关联的信号值，其可以由至少一个电路板描述文件描述，并且可以包括至少一个现场可编程门 阵列仿真电路设计。 所述方法还可以包括处理，所探测的信号值与被仿真的电路设计的一部分相关联，所述仿真接口能够被配置为向至少所述验证模块提供定时和控制信息，并且可以包括控制器和 存储器件，其中控制器能够被配置为接收探测信号值。 该方法还可以包括存储处理后的信息并将其发送到主机工作站。