公开(公告)号：US08724726B2

公开(公告)日：2014-05-13

申请号：US12607626

申请日：2009-10-28

申请人： Hung-Su Park ,  Shin-Woo Kang ,  Soo-Bok Yeo ,  Ki-Hwan Jeon ,  Joo-Kwang Kim ,  Sung-Chul Han

发明人： Hung-Su Park ,  Shin-Woo Kang ,  Soo-Bok Yeo ,  Ki-Hwan Jeon ,  Joo-Kwang Kim ,  Sung-Chul Han

IPC分类号： H04B7/02

CPC分类号： H04W52/52 ,  H04L5/0023 ,  H04L5/0044 ,  H04L5/0064

摘要： An automatic gain control apparatus and method for a compressed mode in a MIMO system are provided. The method includes determining power at a first frequency band using a first receiver, simultaneously determining power at a second frequency band using a second receiver in a compressed mode, if the second receiver changes a power determination frequency band into the first frequency band, correcting the power determination value of the first receiver, and applying the corrected power determination value of the first receiver to the second receiver.

摘要翻译： 提供了一种用于MIMO系统中的压缩模式的自动增益控制装置和方法。 该方法包括使用第一接收机确定第一频带处的功率，同时使用第二接收机以压缩模式确定第二频带处的功率，如果第二接收机将功率确定频带改变为第一频带， 第一接收机的功率确定值，以及将第一接收机的校正功率确定值应用于第二接收机。

公开(公告)号：US07295539B2

公开(公告)日：2007-11-13

申请号：US10426016

申请日：2003-04-30

申请人： Sung-Chul Han ,  Joo-Kwang Kim ,  Chae-Man Lim

发明人： Sung-Chul Han ,  Joo-Kwang Kim ,  Chae-Man Lim

IPC分类号： H04B7/216

CPC分类号： H04B1/7117 ,  H04B1/712

摘要： An apparatus and method for generating reference timings. Each of at least two Node Bs transmits a first channel signal for providing a reference timing and a second channel signal different from the first channel signal and a UE has a plurality of fingers for demodulating the first channel signals. A first timing generator receives an SFN of a reference Node B having a communication link established with the UE, selects a first channel FB timing from a reference finger, and generates an SFN reference timing based on the SFN and the selected first channel FB timing. A second timing generator generates a second channel FB timing to demodulate the second channel signal of the reference Node B from the selected first channel FB timing through offset control. A third timing generator generates an uplink channel FB timing having a predetermined offset from the second channel FB timing.

摘要翻译： 一种用于产生参考定时的装置和方法。 至少两个节点B中的每一个发送用于提供参考定时的第一信道信号和不同于第一信道信号的第二信道信号，并且UE具有用于解调第一信道信号的多个指状物。 第一定时发生器接收具有与UE建立的通信链路的参考节点B的SFN，从参考手指选择第一信道FB定时，并基于SFN和所选择的第一信道FB定时产生SFN参考定时。 第二定时发生器产生第二通道FB定时，以通过偏移控制从所选择的第一通道FB定时解调参考节点B的第二通道信号。 第三定时发生器产生具有来自第二通道FB定时的预定偏移的上行链路信道FB定时。

公开(公告)号：US07155642B2

公开(公告)日：2006-12-26

申请号：US09943895

申请日：2001-08-31

申请人： Sung-Chul Han

发明人： Sung-Chul Han

IPC分类号： G01F11/00 ,  G11C29/00

CPC分类号： H03M13/6569 ,  H03M13/2714 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2957

摘要： An interleaver is disclosed for a turbo encoder in an UMTS. The interleaver includes a register for updating and registering a plurality of parameters for setting an operating condition of the interleaver; a controller for generating a control signal for controlling an operation of the system by receiving the operating condition from the register; an address calculator for generating a finally interleaved address using an inter-row permutation pattern T(j), an intra-row permutation pattern increment arrangement value incr(j) and an intra-row permutation basic sequence s(i), provided from the register according to the control signal generated by the controller; and a data storage for sequentially storing data input to the turbo encoder and outputting data corresponding to the address generated by the address calculator.

公开(公告)号：US20160232125A1

公开(公告)日：2016-08-11

申请号：US15002008

申请日：2016-01-20

申请人： Sung-Chul Han ,  Joon-Won Ko ,  In-Chul Song

发明人： Sung-Chul Han ,  Joon-Won Ko ,  In-Chul Song

IPC分类号： G06F15/167 ,  H04L29/08

CPC分类号： G06F15/167 ,  G06F11/0727 ,  G06F17/30017 ,  G06F17/30371

摘要： A storage device, method for processing a plurality of pieces of client data, and a chipset are provided. The storage device includes a first stage storage unit configured to receive the plurality of pieces of client data generated in bursts from a plurality of clients and store the received plurality of pieces of client data; a second stage storage unit configured to receive the plurality of pieces of client data from the first stage storage unit and store the received plurality of pieces of client data in a plurality of memory banks shared by the plurality of clients, respectively, in bursts; and a third stage storage unit configured to receive each of the plurality of pieces of client data from the second stage storage unit and store data of a transaction unit corresponding to a transmission unit for data processing.

摘要翻译： 提供了一种用于处理多条客户端数据的存储装置，方法和芯片组。 存储装置包括：第一级存储单元，被配置为接收从多个客户端以突发生成的多条客户端数据，并存储所接收的多条客户端数据; 第二级存储单元，被配置为从第一级存储单元接收多条客户端数据，并将所接收的多条客户端数据分别存储在由多个客户端共享的多个存储体中; 以及第三级存储单元，被配置为从所述第二级存储单元接收所述多条客户端数据中的每一条，并存储与用于数据处理的传输单元对应的交易单元的数据。

公开(公告)号：US07039096B2

公开(公告)日：2006-05-02

申请号：US09991514

申请日：2001-11-16

申请人： Sung-Chul Han

发明人： Sung-Chul Han

IPC分类号： H04B1/69 ,  H04B1/10

CPC分类号： H04B1/7115 ,  H04B1/7117 ,  H04B2201/7071

摘要： A rake receiver for high data rate communications systems is provided that is able to share resources between demodulating branches without using independent hardware resources for each finger. The rake receiver of the present invention uses less circuitry while keeping functional equivalence, and it requires relatively smaller additional area when increasing the number of demodulating branches, thereby having a significantly smaller size, being able to track more demodulating paths for increasing performance, and being less complex as compared to conventional rake receivers for high data rate communications systems.

公开(公告)号：US06999719B2

公开(公告)日：2006-02-14

申请号：US10061091

申请日：2002-02-01

申请人： Sung-Chul Han

发明人： Sung-Chul Han

IPC分类号： H04B15/00

CPC分类号： H04B1/7115 ,  H04B1/712 ,  H04B2201/70707

摘要： A symbol combining device for multi-path diversity includes a plurality of demodulation circuits for demodulating received signals, a common memory for storing outputs of the demodulation circuits, a symbol combiner for receiving the outputs of the common memory corresponding to the demodulation circuits and for combining the outputs, and a memory controller for controlling the common memory to timely separate the write and read operations. To timely separate the write and read operations, the memory controller controls the common memory in order that the demodulation circuits sequentially access the common memory and the resultant outputs of the demodulation circuits are written in the common memory, and the symbol combiner reads the outputs of the demodulation circuits written in the common memory sequentially. Because the deskewer of the symbol combining device is constructed of a single memory, not FIFO by channels, the required number of gates is about 40% of the FIFO by channels, and the size of the symbol combining device is reduced to 40%. Further, the symbol combining device can be easily adaptable to change of the number of channels for various services.