公开(公告)号：US6060922A

公开(公告)日：2000-05-09

申请号：US26842

申请日：1998-02-20

申请人： Hwang-Cherng Chow ,  Chi-Chang Shuai ,  Yuan-Hua Chu

发明人： Hwang-Cherng Chow ,  Chi-Chang Shuai ,  Yuan-Hua Chu

IPC分类号： H03K5/04 ,  H03K5/156 ,  H03K3/017

CPC分类号： H03K5/04 ,  H03K5/1565

摘要： A duty cycle control buffer uses an edge detector input stage to detect the transitions of an unpredictable clock signal input. The edge detector generates one shot output signals in synchronism with the clock signal. A pulse width controllable monostable multivibrator converts the one shot signals into rectangular pulses, at the same frequency as the original clock input. The rectangular pulses are inverted and then averaged, to provide a voltage input to one side of an operational amplifier. A reference voltage is supplied to the other side of the operational amplifier, such that the difference between the average voltage and the reference voltage generates an output control voltage from the operational amplifier. This control voltage provides negative feedback to a pulse width control stage within the monostable multivibrator, thereby adjusting the pulse width of the rectangular pulse output until a steady state is reached. A frequency divider circuit may be inserted in front of the edge detector to add a selective frequency dividing capability to the duty cycle control buffer.

摘要翻译： 占空比控制缓冲器使用边沿检测器输入级来检测不可预测的时钟信号输入的转换。 边沿检测器产生与时钟信号同步的单触发输出信号。 脉冲宽度可调单稳态多谐振荡器将单触发信号转换成与原始时钟输入相同频率的矩形脉冲。 将矩形脉冲反相然后平均，以向运算放大器的一侧提供电压输入。 参考电压被提供给运算放大器的另一侧，使得平均电压和参考电压之间的差产生来自运算放大器的输出控制电压。 该控制电压向单稳态多谐振荡器内的脉冲宽度控制级提供负反馈，从而调整矩形脉冲输出的脉冲宽度，直到达到稳定状态。 可以在边缘检测器的前面插入分频器电路，以向占空比控制缓冲器增加选择性分频能力。

公开(公告)号：US06198317B1

公开(公告)日：2001-03-06

申请号：US09393232

申请日：1999-09-09

申请人： Hwang-Cherng Chow ,  Yuan-Hua Chu ,  Chi-Chang Shuai

发明人： Hwang-Cherng Chow ,  Yuan-Hua Chu ,  Chi-Chang Shuai

IPC分类号： H03B1900

CPC分类号： H03K5/00006 ,  H03K3/0307 ,  H03K5/1565

摘要： An N times frequency multiplication circuit uses duty cycle control buffers in combination with edge detectors to provide both multiplication and 50% duty cycle adjustment. Parallel branches of duty cycle control buffers are preset for respective duty cycles of 1/N, 2/N,...,N−1/N. The buffers each receive a common edge detected input signal and simultaneously output their respective duty cycle adjusted clock signals. A rising and falling edge detector generates a pulse train at double the frequency of the 1/N buffer output, while falling edge detectors generate time spaced pulse trains from the outputs of their respective 2/N,...,N−1/N buffers. These pulse trains are combined in an OR gate to provide an output pulse train at a frequency N times the input clock frequency fin. A final stage duty cycle control buffer adjusts the N times fin output signal to a 50% duty cycle.

摘要翻译： N倍频电路使用与边缘检测器组合的占空比控制缓冲器来提供乘法和50％占空比调整。 1 / N，2 / N，...，N-1 / N的占空比的预置占空比控制缓冲器的并行分支。 每个缓冲器都接收公共边沿检测的输入信号，同时输出它们各自的占空比调整的时钟信号。 上升沿和下降沿检测器以1 / N缓冲器输出的频率的两倍产生脉冲串，而下降沿检测器从它们各自的2 / N，...，N-1 / N的输出产生时间间隔的脉冲串 缓冲区 这些脉冲串组合在或门中以提供输入脉冲序列，频率为输入时钟频率fin的N倍。 最后一级占空比控制缓冲器将N次散热片输出信号调整到50％占空比。

公开(公告)号：US08743627B2

公开(公告)日：2014-06-03

申请号：US13352411

申请日：2012-01-18

申请人： Shi-Wen Chen ,  Tsan-Tang Chen ,  Chi-Chang Shuai

发明人： Shi-Wen Chen ,  Tsan-Tang Chen ,  Chi-Chang Shuai

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C7/14

摘要： A memory device comprises a memory cell array, a first and a second pre-charging switch circuits, a selecting circuit, an auxiliary memory cell array, a dynamic voltage controller and a sense amplifier. The auxiliary memory cell array comprises an auxiliary read bit line and a plurality of memory cells arranged in a column and electrically connected to the auxiliary read bit line. The second pre-charging switch circuit determines whether or not to supply a reference voltage to each of the aforementioned memory cells according to a pre-charging control signal. The dynamic voltage controller determines whether or not to supply a voltage to the auxiliary read bit line according to the voltage level of the output signal of the selecting circuit. The sense amplifier compares the voltage levels of the output signal of the selecting circuit and the voltage on the auxiliary read bit line to output a sensing result accordingly.

摘要翻译： 存储器件包括存储单元阵列，第一和第二预充电开关电路，选择电路，辅助存储单元阵列，动态电压控制器和读出放大器。 辅助存储单元阵列包括辅助读位线和布置在列中并电连接到辅助读位线的多个存储单元。 第二预充电开关电路根据预充电控制信号来确定是否向每个上述存储单元提供参考电压。 动态电压控制器根据选择电路的输出信号的电压决定是否向辅助读取位线提供电压。 读出放大器将选择电路的输出信号的电压电平和辅助读取位线上的电压进行比较，从而相应地输出感测结果。

公开(公告)号：US20130182519A1

公开(公告)日：2013-07-18

申请号：US13352411

申请日：2012-01-18

申请人： Shi-Wen CHEN ,  Tsan-Tang Chen ,  Chi-Chang Shuai

发明人： Shi-Wen CHEN ,  Tsan-Tang Chen ,  Chi-Chang Shuai

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C7/14

摘要： A memory device comprises a memory cell array, a first and a second pre-charging switch circuits, a selecting circuit, an auxiliary memory cell array, a dynamic voltage controller and a sense amplifier. The auxiliary memory cell array comprises an auxiliary read bit line and a plurality of memory cells arranged in a column and electrically connected to the auxiliary read bit line. The second pre-charging switch circuit determines whether or not to supply a reference voltage to each of the aforementioned memory cells according to a pre-charging control signal. The dynamic voltage controller determines whether or not to supply a voltage to the auxiliary read bit line according to the voltage level of the output signal of the selecting circuit. The sense amplifier compares the voltage levels of the output signal of the selecting circuit and the voltage on the auxiliary read bit line to output a sensing result accordingly.

摘要翻译： 存储器件包括存储单元阵列，第一和第二预充电开关电路，选择电路，辅助存储单元阵列，动态电压控制器和读出放大器。 辅助存储单元阵列包括辅助读位线和布置在列中并电连接到辅助读位线的多个存储单元。 第二预充电开关电路根据预充电控制信号来确定是否向每个上述存储单元提供参考电压。 动态电压控制器根据选择电路的输出信号的电压决定是否向辅助读取位线提供电压。 读出放大器将选择电路的输出信号的电压电平和辅助读取位线上的电压进行比较，从而相应地输出感测结果。