公开(公告)号：US06198317B1

公开(公告)日：2001-03-06

申请号：US09393232

申请日：1999-09-09

申请人： Hwang-Cherng Chow ,  Yuan-Hua Chu ,  Chi-Chang Shuai

发明人： Hwang-Cherng Chow ,  Yuan-Hua Chu ,  Chi-Chang Shuai

IPC分类号： H03B1900

CPC分类号： H03K5/00006 ,  H03K3/0307 ,  H03K5/1565

摘要： An N times frequency multiplication circuit uses duty cycle control buffers in combination with edge detectors to provide both multiplication and 50% duty cycle adjustment. Parallel branches of duty cycle control buffers are preset for respective duty cycles of 1/N, 2/N,...,N−1/N. The buffers each receive a common edge detected input signal and simultaneously output their respective duty cycle adjusted clock signals. A rising and falling edge detector generates a pulse train at double the frequency of the 1/N buffer output, while falling edge detectors generate time spaced pulse trains from the outputs of their respective 2/N,...,N−1/N buffers. These pulse trains are combined in an OR gate to provide an output pulse train at a frequency N times the input clock frequency fin. A final stage duty cycle control buffer adjusts the N times fin output signal to a 50% duty cycle.

摘要翻译： N倍频电路使用与边缘检测器组合的占空比控制缓冲器来提供乘法和50％占空比调整。 1 / N，2 / N，...，N-1 / N的占空比的预置占空比控制缓冲器的并行分支。 每个缓冲器都接收公共边沿检测的输入信号，同时输出它们各自的占空比调整的时钟信号。 上升沿和下降沿检测器以1 / N缓冲器输出的频率的两倍产生脉冲串，而下降沿检测器从它们各自的2 / N，...，N-1 / N的输出产生时间间隔的脉冲串 缓冲区 这些脉冲串组合在或门中以提供输入脉冲序列，频率为输入时钟频率fin的N倍。 最后一级占空比控制缓冲器将N次散热片输出信号调整到50％占空比。

公开(公告)号：US6060922A

公开(公告)日：2000-05-09

申请号：US26842

申请日：1998-02-20

申请人： Hwang-Cherng Chow ,  Chi-Chang Shuai ,  Yuan-Hua Chu

发明人： Hwang-Cherng Chow ,  Chi-Chang Shuai ,  Yuan-Hua Chu

IPC分类号： H03K5/04 ,  H03K5/156 ,  H03K3/017

CPC分类号： H03K5/04 ,  H03K5/1565

摘要： A duty cycle control buffer uses an edge detector input stage to detect the transitions of an unpredictable clock signal input. The edge detector generates one shot output signals in synchronism with the clock signal. A pulse width controllable monostable multivibrator converts the one shot signals into rectangular pulses, at the same frequency as the original clock input. The rectangular pulses are inverted and then averaged, to provide a voltage input to one side of an operational amplifier. A reference voltage is supplied to the other side of the operational amplifier, such that the difference between the average voltage and the reference voltage generates an output control voltage from the operational amplifier. This control voltage provides negative feedback to a pulse width control stage within the monostable multivibrator, thereby adjusting the pulse width of the rectangular pulse output until a steady state is reached. A frequency divider circuit may be inserted in front of the edge detector to add a selective frequency dividing capability to the duty cycle control buffer.

摘要翻译： 占空比控制缓冲器使用边沿检测器输入级来检测不可预测的时钟信号输入的转换。 边沿检测器产生与时钟信号同步的单触发输出信号。 脉冲宽度可调单稳态多谐振荡器将单触发信号转换成与原始时钟输入相同频率的矩形脉冲。 将矩形脉冲反相然后平均，以向运算放大器的一侧提供电压输入。 参考电压被提供给运算放大器的另一侧，使得平均电压和参考电压之间的差产生来自运算放大器的输出控制电压。 该控制电压向单稳态多谐振荡器内的脉冲宽度控制级提供负反馈，从而调整矩形脉冲输出的脉冲宽度，直到达到稳定状态。 可以在边缘检测器的前面插入分频器电路，以向占空比控制缓冲器增加选择性分频能力。

公开(公告)号：US08384455B2

公开(公告)日：2013-02-26

申请号：US13114030

申请日：2011-05-23

申请人： Yu Lee ,  Nai-Chen Cheng ,  Ji-Jan Chen ,  Yuan-Hua Chu ,  Ching-Yuan Yang

发明人： Yu Lee ,  Nai-Chen Cheng ,  Ji-Jan Chen ,  Yuan-Hua Chu ,  Ching-Yuan Yang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G06F1/10 ,  G06F1/12 ,  H03L7/07 ,  H03L7/0812 ,  H04L7/0008

摘要： An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.

摘要翻译： 提供了一种用于时钟偏移补偿的装置。 该装置包括设置在第一管芯中的第一延迟锁定环（DLL）模块和设置在第二管芯中的第二DLL模块。 第一DLL模块的第一输入端接收参考时钟。 第二DLL模块的第一输入端电连接到第一DLL模块的输出端。 第二DLL模块的输出端电连接到第一DLL模块的第二输入端。

公开(公告)号：US20110068841A1

公开(公告)日：2011-03-24

申请号：US12923435

申请日：2010-09-21

申请人： Hong-Yi Huang ,  Jen-Chieh Liu ,  Yuan-Hua Chu

发明人： Hong-Yi Huang ,  Jen-Chieh Liu ,  Yuan-Hua Chu

IPC分类号： H03L7/06

CPC分类号： H03L7/0991 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/1534 ,  H03K2005/00071 ,  H03K2005/00293 ,  H03L2207/50

摘要： A digitally controlled oscillator (DCO) includes a pulse generator for generating a pulse signal upon an edge of a trigger signal, and at least one delay circuit coupled to delay the pulse signal generated by the pulse generator. The pulse generator is coupled to receive one of the delayed pulse signal from the at least one delay circuit and an enable signal as the trigger signal. A digitally controlled varactor (DCV) includes a transistor having a gate, a source, a drain, and a substrate, wherein at least one of the gate, the source, the drain, and the substrate is coupled to receive one of two or more voltages, wherein at least one of the two or more voltages is not a power supply voltage or ground.

摘要翻译： 数字控制振荡器（DCO）包括脉冲发生器，用于在触发信号的边沿产生脉冲信号，以及至少一个延迟电路，其被连接以延迟由脉冲发生器产生的脉冲信号。 脉冲发生器被耦合以接收来自至少一个延迟电路的延迟脉冲信号中的一个和使能信号作为触发信号。 数字控制变容二极管（DCV）包括具有栅极，源极，漏极和衬底的晶体管，其中栅极，源极，漏极和衬底中的至少一个被耦合以接收两个或更多个中的一个 电压，其中所述两个或更多个电压中的至少一个不是电源电压或接地。

公开(公告)号：US07859343B2

公开(公告)日：2010-12-28

申请号：US11595972

申请日：2006-11-13

申请人： Hong-Yi Huang ,  Jen-Chieh Liu ,  Yuan-Hua Chu

发明人： Hong-Yi Huang ,  Jen-Chieh Liu ,  Yuan-Hua Chu

IPC分类号： H03L7/08

CPC分类号： H03L7/0991 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/1534 ,  H03K2005/00071 ,  H03K2005/00293 ,  H03L2207/50

摘要： A digitally controlled oscillator (DCO) includes a pulse generator for generating a pulse signal upon an edge of a trigger signal, and at least one delay circuit coupled to delay the pulse signal generated by the pulse generator. The pulse generator is coupled to receive one of the delayed pulse signal from the at least one delay circuit and an enable signal as the trigger signal. A digitally controlled varactor (DCV) includes a transistor having a gate, a source, a drain, and a substrate, wherein at least one of the gate, the source, the drain, and the substrate is coupled to receive one of two or more voltages, wherein at least one of the two or more voltages is not a power supply voltage or ground.

摘要翻译： 数字控制振荡器（DCO）包括脉冲发生器，用于在触发信号的边沿产生脉冲信号，以及至少一个延迟电路，其被连接以延迟由脉冲发生器产生的脉冲信号。 脉冲发生器被耦合以接收来自至少一个延迟电路的延迟脉冲信号中的一个和使能信号作为触发信号。 数字控制变容二极管（DCV）包括具有栅极，源极，漏极和衬底的晶体管，其中栅极，源极，漏极和衬底中的至少一个被耦合以接收两个或更多个中的一个 电压，其中所述两个或更多个电压中的至少一个不是电源电压或接地。

公开(公告)号：US20080111641A1

公开(公告)日：2008-05-15

申请号：US11595972

申请日：2006-11-13

申请人： Hong-Yi Huang ,  Jen-Chieh Liu ,  Yuan-Hua Chu

发明人： Hong-Yi Huang ,  Jen-Chieh Liu ,  Yuan-Hua Chu

IPC分类号： H03L7/08 ,  H01L29/94 ,  H03B28/00

CPC分类号： H03L7/0991 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/1534 ,  H03K2005/00071 ,  H03K2005/00293 ,  H03L2207/50

摘要： A digitally controlled oscillator (DCO) includes a pulse generator for generating a pulse signal upon an edge of a trigger signal, and at least one delay circuit coupled to delay the pulse signal generated by the pulse generator. The pulse generator is coupled to receive one of the delayed pulse signal from the at least one delay circuit and an enable signal as the trigger signal. A digitally controlled varactor (DCV) includes a transistor having a gate, a source, a drain, and a substrate, wherein at least one of the gate, the source, the drain, and the substrate is coupled to receive one of two or more voltages, wherein at least one of the two or more voltages is not a power supply voltage or ground.

摘要翻译： 数字控制振荡器（DCO）包括脉冲发生器，用于在触发信号的边沿产生脉冲信号，以及至少一个延迟电路，其被连接以延迟由脉冲发生器产生的脉冲信号。 脉冲发生器被耦合以接收来自至少一个延迟电路的延迟脉冲信号中的一个和使能信号作为触发信号。 数字控制变容二极管（DCV）包括具有栅极，源极，漏极和衬底的晶体管，其中栅极，源极，漏极和衬底中的至少一个被耦合以接收两个或更多个中的一个 电压，其中所述两个或更多个电压中的至少一个不是电源电压或接地。

公开(公告)号：US08972699B2

公开(公告)日：2015-03-03

申请号：US12107082

申请日：2008-04-22

申请人： Tai-Ji Lin ,  Tien-Wei Hsieh ,  Yuan-Hua Chu ,  Shih-Hao Ou ,  Xiang-Sheng Deng ,  Chih-Wei Liu

发明人： Tai-Ji Lin ,  Tien-Wei Hsieh ,  Yuan-Hua Chu ,  Shih-Hao Ou ,  Xiang-Sheng Deng ,  Chih-Wei Liu

IPC分类号： G06F9/30 ,  G06F9/50 ,  G06F9/38

CPC分类号： G06F9/505 ,  G06F9/3877 ,  G06F2209/5017

摘要： A multicore interface with dynamic task management capability and a task loading and offloading method thereof are provided. The method disposes a communication interface between a micro processor unit (MPU) and a digital signal processor (DSP) and dynamically manages tasks assigned by the MPU to the DSP. First, an idle processing unit of the DSP is searched, and then one of a plurality of threads of the task is assigned to the processing unit. Finally, the processing unit is activated to execute the thread. Accordingly, the communication efficiency of the multicore processor can be effectively increased while the hardware cost can be saved.

摘要翻译： 提供了具有动态任务管理功能的多核接口及其任务加载和卸载方法。 该方法在微处理器单元（MPU）和数字信号处理器（DSP）之间配置通信接口，动态管理由MPU分配给DSP的任务。 首先，搜索DSP的空闲处理单元，然后将任务的多个线程中的一个分配给处理单元。 最后，处理单元被激活以执行线程。 因此，可以有效地提高多核处理器的通信效率，同时可以节省硬件成本。

公开(公告)号：US20090212822A1

公开(公告)日：2009-08-27

申请号：US12141112

申请日：2008-06-18

申请人： Hong-Yi Huang ,  Chun-Tsai Hung ,  Yuan-Hua Chu

发明人： Hong-Yi Huang ,  Chun-Tsai Hung ,  Yuan-Hua Chu

IPC分类号： H03K19/094

CPC分类号： H03K19/086 ,  H03K19/20

摘要： A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed by a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier generates a first output signal and a second output signal according to the first current and the second current.

摘要翻译： 公开了一种电流开关逻辑电路。 该电路包括由第一晶体管至第五晶体管形成的电流检测放大器和逻辑树。 逻辑树用于生成第一个电流和第二个电流。 电流检测放大器根据第一电流和第二电流产生第一输出信号和第二输出信号。

公开(公告)号：US07522084B2

公开(公告)日：2009-04-21

申请号：US11826339

申请日：2007-07-13

申请人： Hong-Yi Huang ,  Sheng-Dar Wu ,  Yuan-Hua Chu

发明人： Hong-Yi Huang ,  Sheng-Dar Wu ,  Yuan-Hua Chu

IPC分类号： H03M1/60

CPC分类号： G04F10/005

摘要： A cycle time to digital converter includes a dual delay lock loop, multi phase sampling detector and VDL sampling detector. The dual delay lock loop generates the first voltage corresponding to the first delay time and the second voltage corresponding to the second delay time. The multi phase sampling detector receives first start signal, first stop signal and first voltage to detect a coarse delay time, generates the first group signals according to the coarse delay time, delays the first stop signal by a common delay time to generate the second stop signal, and delays the first start signal by the coarse delay time and the common delay time to generate the second start signal. The VDL sampling detector receives first voltage, second voltage, second start signal and second stop signal for detecting a fine delay time and generates the second group signals according to the fine delay time.

摘要翻译： 数字转换器的周期时间包括双延迟锁定环路，多相采样检测器和VDL采样检测器。 双延迟锁定环路产生对应于第一延迟时间的第一电压和对应于第二延迟时间的第二电压。 多相采样检测器接收第一起始信号，第一停止信号和第一电压以检测粗延迟时间，根据粗延迟时间产生第一组信号，将第一停止信号延迟公共延迟时间以产生第二停止 并且将第一起始信号延迟粗延迟时间和公共延迟时间以产生第二起始信号。 VDL采样检测器接收第一电压，第二电压，第二起始信号和第二停止信号，用于检测精细的延迟时间，并根据微小的延迟时间产生第二组信号。

公开(公告)号：US07466177B2

公开(公告)日：2008-12-16

申请号：US11491159

申请日：2006-07-24

申请人： Hong-Yi Huang ,  Wei-Ming Chiu ,  Yuan-Hua Chu

发明人： Hong-Yi Huang ,  Wei-Ming Chiu ,  Yuan-Hua Chu

IPC分类号： H03K3/17

CPC分类号： H03K5/151 ,  H03K5/1565

摘要： A pulse-width control loop (PWCL) for clock with any pulse-width ratio within a wide range is provided. A differential programmable charge pump is employed to stabilize the current source by complementary connection. The differential programmable charge pump has a pair of differential charge pumps and a current source module to adjust the ratio of charge to discharge, so as to accelerate the range of the adjustable pulse-width ratio of the output clock and increase the output resolution. Further, a ratioless input control stage is employed to simplify the circuit design and avoid static power consumption. Moreover, the control stage adjusts rising pulse width and dropping pulse width at one period, thereby accelerating the lock speed and the range of the adjustable pulse-width ratio (i.e., duty cycle) of the input clock.

摘要翻译： 提供了在宽范围内具有任何脉冲宽度比的时钟的脉冲宽度控制回路（PWCL）。 采用差分可编程电荷泵通过互补连接来稳定电流源。 差分可编程电荷泵具有一对差动电荷泵和电流源模块，用于调节充放电比例，从而加快输出时钟可调脉宽比的范围，提高输出分辨率。 此外，采用无竞争的输入控制级以简化电路设计并避免静态功耗。 此外，控制级在一个周期调节上升脉冲宽度和下降脉冲宽度，从而加速锁定速度和输入时钟的可调脉冲宽度比（即占空比）的范围。