公开(公告)号：US20120113375A1

公开(公告)日：2012-05-10

申请号：US13355398

申请日：2012-01-20

申请人： Hye-Seok NA ,  Byoung-Sun NA ,  Won-Hee LEE ,  Ho-Kyoon KWON ,  Ji-Hyun KWON

发明人： Hye-Seok NA ,  Byoung-Sun NA ,  Won-Hee LEE ,  Ho-Kyoon KWON ,  Ji-Hyun KWON

IPC分类号： G02F1/1343

CPC分类号： G02F1/133707

摘要： A first slit pattern is formed in a display substrate and a display panel of vertical alignment mode having the display substrate. The first slit pattern includes slits, a pair of projections and a pair of notches. A divergence point where the slits meet each other and an incision portion of the slits have the same function as the pair of projections in the generation of a singular point of liquid crystal. A contact hole exposing a part of an output electrode of a switching element is formed at a protective layer of an array substrate. A step recess is formed at a protective layer corresponding to a storage electrode, a divergence point of the slits is arranged to correspond to the storage electrode. The singular point of the liquid crystal is induced to occur at a regular position, and thus afterimages and spots can be prevented.

摘要翻译： 在显示基板和具有显示基板的垂直取向模式的显示面板上形成第一狭缝图案。 第一狭缝图案包括狭缝，一对突起和一对凹口。 狭缝在彼此相遇并且狭缝的切口部分的发散点在产生液晶的奇异点时具有与该对突起相同的功能。 在阵列基板的保护层上形成露出开关元件的输出电极的一部分的接触孔。 在对应于存储电极的保护层上形成台阶凹槽，狭缝的发散点被布置成对应于存储电极。 液晶的奇异点被诱发发生在规则位置，因此可以防止残影和斑点。

公开(公告)号：US20090290114A1

公开(公告)日：2009-11-26

申请号：US12418873

申请日：2009-04-06

申请人： Hye-Seok NA ,  Byoung-Sun NA ,  Won-Hee LEE ,  Ho-Kyoon KWON ,  Ji-Hyun KWON

发明人： Hye-Seok NA ,  Byoung-Sun NA ,  Won-Hee LEE ,  Ho-Kyoon KWON ,  Ji-Hyun KWON

IPC分类号： G02F1/1343

CPC分类号： G02F1/133707

摘要： A first slit pattern is formed in a display substrate and a display panel of vertical alignment mode having the display substrate. The first slit pattern includes slits, a pair of projections and a pair of notches. A divergence point where the slits meet each other and an incision portion of the slits have the same function as the pair of projections in the generation of a singular point of liquid crystal. A contact hole exposing a part of an output electrode of a switching element is formed at a protective layer of an array substrate. A step recess is formed at a protective layer corresponding to a storage electrode, a divergence point of the slits is arranged to correspond to the storage electrode. The singular point of the liquid crystal is induced to occur at a regular position, and thus afterimages and spots can be prevented.

摘要翻译： 在显示基板和具有显示基板的垂直取向模式的显示面板上形成第一狭缝图案。 第一狭缝图案包括狭缝，一对突起和一对凹口。 狭缝在彼此相遇并且狭缝的切口部分的发散点在产生液晶的奇异点时具有与该对突起相同的功能。 在阵列基板的保护层上形成露出开关元件的输出电极的一部分的接触孔。 在对应于存储电极的保护层上形成台阶凹槽，狭缝的发散点被布置成对应于存储电极。 液晶的奇异点被诱发发生在规则位置，因此可以防止残影和斑点。

公开(公告)号：US20100208157A1

公开(公告)日：2010-08-19

申请号：US12507764

申请日：2009-07-22

申请人： Ji-Hyun KWON ,  Hey-Seok NA ,  Won-Hee LEE ,  Ho-Kyoon KWON ,  Byoung-Sun NA ,  Dong-Yoon LEE ,  Ju-Hee LEE ,  Gwang-Bum KO

发明人： Ji-Hyun KWON ,  Hey-Seok NA ,  Won-Hee LEE ,  Ho-Kyoon KWON ,  Byoung-Sun NA ,  Dong-Yoon LEE ,  Ju-Hee LEE ,  Gwang-Bum KO

IPC分类号： G02F1/1368 ,  G02F1/13

CPC分类号： G02F1/136286 ,  G02F1/134363 ,  G02F2001/134345 ,  G09G2300/0426 ,  G09G2300/0439 ,  G09G2320/0209

摘要： A liquid crystal display (LCD), according to an exemplary embodiment of the present invention, includes a plurality of pixels arranged in a matrix shape. Each of the pixels include a first subpixel and a second subpixel. The pixels include a first thin film transistor transmitting a first data voltage to the first subpixel. The first thin film transistor includes a first source electrode, a first drain electrode, and a first gate electrode. The pixels include a second thin film transistor transmitting a second data voltage to the second subpixel. The second thin film transistor includes a second source electrode, a second drain electrode, and a second gate electrode. A relative position of the first drain electrode with respect to the first source electrode is opposite to a relative position of the second drain electrode with respect to the second source electrode in each pixel.

摘要翻译： 根据本发明的示例性实施例的液晶显示器（LCD）包括以矩阵形状排列的多个像素。 每个像素包括第一子像素和第二子像素。 像素包括向第一子像素发送第一数据电压的第一薄膜晶体管。 第一薄膜晶体管包括第一源电极，第一漏电极和第一栅电极。 像素包括向第二子像素传输第二数据电压的第二薄膜晶体管。 第二薄膜晶体管包括第二源电极，第二漏电极和第二栅电极。 第一漏电极相对于第一源电极的相对位置与第二漏电极相对于每个像素中的第二源电极的相对位置相反。

公开(公告)号：US20100007653A1

公开(公告)日：2010-01-14

申请号：US12333561

申请日：2008-12-12

申请人： Soon-Il AHN ,  Ho-Kyoon KWON ,  Byoung-Sun NA ,  Dong-Hyon KI ,  Seung-Soo BAEK ,  Hye-Seok NA

发明人： Soon-Il AHN ,  Ho-Kyoon KWON ,  Byoung-Sun NA ,  Dong-Hyon KI ,  Seung-Soo BAEK ,  Hye-Seok NA

IPC分类号： G09G3/36 ,  G06F3/038

CPC分类号： G09G3/3677 ,  G09G2330/08 ,  G11C19/184 ,  G11C19/28

摘要： A gate driver that comprises n shift registers, wherein n is an integer equal to or larger than 1, each of the n shift registers includes; a start stage which outputs a gate signal and starts its operation in response to a start signal, and a plurality of subsequent stages which are connected to each other in sequence, and which sequentially output a plurality of gate signals in response to a signal output from the start stage, wherein at least one stage of the plurality of subsequent stages is reset by the start signal.

摘要翻译： 一种包括n个移位寄存器的栅极驱动器，其中n是等于或大于1的整数，n个移位寄存器中的每一个包括： 开始阶段，其响应于起始信号输出门信号并开始其操作;以及多个后续级，它们依次相互连接，并且响应于从...输出的信号顺序地输出多个门信号 起始阶段，其中多个后续级中的至少一级由起始信号复位。

公开(公告)号：US20100013823A1

公开(公告)日：2010-01-21

申请号：US12351095

申请日：2009-01-09

申请人： Ji-Hyun KWON ,  Ho-Kyoon KWON ,  Dong-Hyon KI ,  Won-Hee LEE

发明人： Ji-Hyun KWON ,  Ho-Kyoon KWON ,  Dong-Hyon KI ,  Won-Hee LEE

IPC分类号： G06F3/038

CPC分类号： G09G3/3674 ,  G09G2310/0286 ,  G09G2320/043 ,  G11C19/184

摘要： In the display apparatus, a gate driver receives at least one clock to sequentially provide gate lines in a display panel with a gate signal in a high state corresponding to a high interval of the clock. The gate driver includes a plurality of amorphous silicon transistors and is formed in the display panel through a thin film process. The clock has a delay time of about 2.0 μs or less. If the delay time of the clock is reduced less than about 2.0 μs, a threshold voltage margin of the transistors increases, so that the gate driver may not malfunction in a high temperature aging process. As a result, the gate driver may be prevented from malfunctioning in the high temperature aging process.

摘要翻译： 在显示装置中，栅极驱动器接收至少一个时钟，以在显示面板中依次提供具有对应于时钟的高间隔的高状态的门信号的栅极线。 栅极驱动器包括多个非晶硅晶体管，并通过薄膜工艺形成在显示面板中。 时钟的延迟时间约为2.0个或更少。 如果时钟的延迟时间减小到小于约2.0微米，则晶体管的阈值电压裕度增加，使得栅极驱动器在高温老化过程中可能不会发生故障。 结果，可以防止栅极驱动器在高温老化处理中发生故障。

公开(公告)号：US20100134399A1

公开(公告)日：2010-06-03

申请号：US12423995

申请日：2009-04-15

申请人： Dong-Hyeon KI ,  Ho-Kyoon KWON ,  Ju-Hee LEE ,  Byoung-Sun NA

发明人： Dong-Hyeon KI ,  Ho-Kyoon KWON ,  Ju-Hee LEE ,  Byoung-Sun NA

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28

摘要： A method of driving a gate line includes: charging one of a scan start signal and a carry signal provided from a previous stage to a first node of a present stage; outputting a gate signal through a gate node of the present stage by pulling up a high level of a first clock signal at the first node to boost up a voltage potential of the first node; discharging the voltage potential of the first node and a voltage potential of the gate node to hold the first node and the gate node at a first power voltage as the first clock signal is shifted to a low level; and receiving a voltage potential signal of a second node of the previous stage, the second node holding a gate signal outputted from the previous stage, to reduce a ripple generated at the first node.

摘要翻译： 驱动栅极线的方法包括：将扫描开始信号和从前一级提供的进位信号中的一个充电到当前级的第一个节点; 通过在第一节点处拉高高电平的第一时钟信号，通过当前级的门节点输出门信号，以升高第一节点的电压电位; 当第一时钟信号被转换到低电平时，放电第一节点的电压和门节点的电压电位，以将第一节点和门节点保持在第一电源电压; 并且接收前一级的第二节点的电压电位信号，所述第二节点保持从前一级输出的门信号，以减少在第一节点处产生的纹波。

公开(公告)号：US20120154308A1

公开(公告)日：2012-06-21

申请号：US13299587

申请日：2011-11-18

申请人： Sang-Jin JEON ,  Ho-Kyoon KWON

发明人： Sang-Jin JEON ,  Ho-Kyoon KWON

IPC分类号： G06F3/041 ,  G09G3/36

CPC分类号： G06F3/0412 ,  G02F1/13338 ,  G02F1/133707 ,  G02F1/13624 ,  G02F2001/134318 ,  G02F2001/134345 ,  G02F2001/134381 ,  H01L29/41733

摘要： A touch display substrate includes a first data line, a first gate line, a first pixel electrode, a second gate line, a second pixel electrode, a senor data line and a first sensor electrode. The first data line extends along a first direction. The first gate line extends along a second direction. The first pixel electrode is electrically connected to the first data line and the first gate line. The second gate line is substantially parallel with the first gate line. The second pixel electrode is adjacent to the first pixel electrode and electrically connected to the first data line and the second gate line. The sensor data line is adjacent to the second pixel electrode and substantially parallel to the first data line. The first sensor electrode is electrically connected to the sensor data line.

摘要翻译： 触摸显示基板包括第一数据线，第一栅极线，第一像素电极，第二栅极线，第二像素电极，传感数据线和第一传感器电极。 第一数据线沿着第一方向延伸。 第一栅极线沿第二方向延伸。 第一像素电极电连接到第一数据线和第一栅极线。 第二栅极线基本上与第一栅极线平行。 第二像素电极与第一像素电极相邻并且电连接到第一数据线和第二栅极线。 传感器数据线与第二像素电极相邻并且基本上平行于第一数据线。 第一传感器电极电连接到传感器数据线。

公开(公告)号：US20120081274A1

公开(公告)日：2012-04-05

申请号：US13016438

申请日：2011-01-28

申请人： Jong-Woong CHANG ,  Ho-Kyoon KWON ,  Shin-Tack KANG

发明人： Jong-Woong CHANG ,  Ho-Kyoon KWON ,  Shin-Tack KANG

IPC分类号： G09G3/36 ,  H01L21/30

CPC分类号： G02F1/136259 ,  G02F1/136213 ,  G02F1/136286 ,  G02F2001/136263 ,  H01L27/1255 ,  H01L29/41733 ,  H01L29/786

摘要： The present invention relates to a thin film transistor array panel, a liquid crystal display, and a method capable of reducing an effect on neighboring pixels in a process of repairing a pixel defect. The thin film transistor array panel may include: a thin film transistor connected to a gate line and a data line to define a pixel area; a pixel electrode formed in the pixel area and connected to the thin film transistor; and a storage electrode including a first portion overlapping the data line between two adjacent gate lines. The storage electrode may also include a second portion connected to the first portion and enclosing an edge of the pixel area except for a region where the first portion is formed. The storage electrode may be branched between pixel electrodes respectively formed in two adjacent pixel areas.

摘要翻译： 本发明涉及一种薄膜晶体管阵列面板，液晶显示器和能够在修复像素缺陷的过程中减少对相邻像素的影响的方法。 薄膜晶体管阵列面板可以包括：连接到栅极线和限定像素区域的数据线的薄膜晶体管; 像素电极，其形成在所述像素区域中并连接到所述薄膜晶体管; 以及存储电极，其包括与两个相邻栅极线之间的数据线重叠的第一部分。 存储电极还可以包括连接到第一部分并且包围除了形成第一部分的区域之外的像素区域的边缘的第二部分。 存储电极可以在分别形成在两个相邻像素区域中的像素电极之间分支。

公开(公告)号：US20090296010A1

公开(公告)日：2009-12-03

申请号：US12470719

申请日：2009-05-22

申请人： Dong-Gyu KIM ,  Ho-Kyoon KWON

发明人： Dong-Gyu KIM ,  Ho-Kyoon KWON

IPC分类号： G02F1/1343

CPC分类号： G02F1/136213

摘要： A display apparatus includes a storage line, a main-storage electrode branched from the storage line, and sub-storage electrodes branched from the main-storage electrode. The main-storage electrode and the sub-storage electrodes form storage capacitors with a pixel electrode. The main-storage electrode has a structure that is suitable for improving an aperture ratio of the display apparatus, and the sub-storage electrodes has a structure that is suitable for improving a driving capability of the display apparatus. Thus, a desired aperture ratio and a desired driving capability may be obtained by adjusting lengths of the main-storage electrode and the sub-storage electrodes.

摘要翻译： 显示装置包括存储线，从存储线分支的主存储电极和从主存储电极分支的副存储电极。 主存储电极和副存储电极形成具有像素电极的存储电容器。 主存储电极具有适于提高显示装置的开口率的结构，并且副存储电极具有适于提高显示装置的驱动能力的结构。 因此，可以通过调节主存储电极和副存储电极的长度来获得期望的开口率和期望的驱动能力。

公开(公告)号：US20110089423A1

公开(公告)日：2011-04-21

申请号：US12829272

申请日：2010-07-01

申请人： Ho-Kyoon KWON

发明人： Ho-Kyoon KWON

IPC分类号： H01L27/06 ,  H01L29/786 ,  H01L23/544

CPC分类号： H01L27/12 ,  H01L23/544 ,  H01L27/124 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film transistor array panel can include: a substrate; a gate line formed on the substrate; a gate pad formed at an end of the gate line; a gate identification member corresponding to the gate pad and formed in the same layer as the gate pad; a gate insulating layer covering the gate line and the gate identification member; a data line formed on the gate insulating layer; a passivation layer formed on the gate insulating layer and the data line; a gate contact assistant formed on the passivation layer; and a gate driving chip electrically connected to the gate contact assistant, wherein the gate contact assistant at least partially overlaps the gate identification member. The gate identification member is formed without producing a step in the gate contact assistant, reducing the risk of defects when wires or other objects are pressed onto the gate pad.

摘要翻译： 薄膜晶体管阵列面板可以包括：基板; 形成在基板上的栅极线; 栅极焊盘，形成在栅极线的端部; 栅极识别构件对应于栅极焊盘并形成在与栅极焊盘相同的层中; 覆盖栅极线和栅极识别构件的栅极绝缘层; 形成在所述栅极绝缘层上的数据线; 形成在栅极绝缘层和数据线上的钝化层; 形成在钝化层上的栅极接触助剂; 以及栅极驱动芯片，其电连接到所述栅极接触辅助件，其中所述栅极接触辅助件至少部分地与所述栅极识别构件重叠。 栅极识别构件形成为不在栅极接触辅助件中产生台阶，从而减少当导线或其它物体被压在门板上时的缺陷的风险。