摘要:
A scan driver for an organic light emitting display includes logic circuitry to receive a plurality of start pulses and either a first clock or a second clock that is an inversion of the first clock and to generate one or more pulse signals as scan signals for driving the sub-pixels of the organic light emitting display panel, where one or more of the pulse signals are delayed by ½ horizontal time from at least another one of the pulse signals.
摘要:
A scan driver for an organic light emitting display includes logic circuitry to receive a plurality of start pulses and either a first clock or a second clock that is an inversion of the first clock and to generate one or more pulse signals as scan signals for driving the sub-pixels of the organic light emitting display panel, where one or more of the pulse signals are delayed by ½ horizontal time from at least another one of the pulse signals.
摘要:
An organic light emitting diode (OLED) display is disclosed. The OLED display includes a display panel including a plurality of pairs of data lines, a plurality of gate line groups crossing the pairs of data lines, and a plurality of pixels each having a drive thin film transistor (TFT) and an organic light emitting diode at each of crossings of the pairs of data lines and the gate line groups, a timing controller generating a non-overlap signal, and a sample and hold block that removes an overlap period between adjacently generated first holding clocks using the non-overlap signal to generate second holding clocks that do not overlap each other, applies sampled threshold voltages of the drive TFTs of the pixels to an output node in response to the second holding clocks, and discharges the output node in the overlap period in response to the non-overlap signal.
摘要:
A gamma reference voltage generation circuit and a flat panel display using the same are provided. The gamma reference voltage generation circuit includes R, G and B gamma reference voltage generators each having a plurality of digital-to-analog converters (DACs) that generate a plurality of R, G and B gamma reference voltages. In the DACs of each of the R, G and B gamma reference voltage generators, a high potential bias voltage input terminal of an uppermost DAC used to generate a gamma reference voltage of a maximum gray level is connected to a high potential voltage source. A high potential bias voltage input terminal of each of remaining DACs except the uppermost DAC is cascade-connected to an output terminal of an upper DAC next to each of the remaining DACs.
摘要:
A gamma reference voltage generation circuit and a flat panel display using the same are provided. The gamma reference voltage generation circuit includes R, G and B gamma reference voltage generators each having a plurality of digital-to-analog converters (DACs) that generate a plurality of R, G and B gamma reference voltages. In the DACs of each of the R, G and B gamma reference voltage generators, a high potential bias voltage input terminal of an uppermost DAC used to generate a gamma reference voltage of a maximum gray level is connected to a high potential voltage source. A high potential bias voltage input terminal of each of remaining DACs except the uppermost DAC is cascade-connected to an output terminal of an upper DAC next to each of the remaining DACs.
摘要:
An organic light emitting diode (OLED) display is disclosed. The OLED display includes a display panel including a plurality of pairs of data lines, a plurality of gate line groups crossing the pairs of data lines, and a plurality of pixels each having a drive thin film transistor (TFT) and an organic light emitting diode at each of crossings of the pairs of data lines and the gate line groups, a timing controller generating a non-overlap signal, and a sample and hold block that removes an overlap period between adjacently generated first holding clocks using the non-overlap signal to generate second holding clocks that do not overlap each other, applies sampled threshold voltages of the drive TFTs of the pixels to an output node in response to the second holding clocks, and discharges the output node in the overlap period in response to the non-overlap signal.