公开(公告)号：US20080205174A1

公开(公告)日：2008-08-28

申请号：US12071552

申请日：2008-02-22

Applicant: Hyong-yong Lee ,  Chan-sub Jun

Inventor： Hyong-yong Lee ,  Chan-sub Jun

IPC: G11C29/00

CPC classification number: G11C29/32 ,  G11C11/401 ,  G11C29/14

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

Abstract translation: 实施例公开半导体存储器件及其测试方法。 半导体存储器件包括在正常工作模式下以第一数据速率提供第一和第二数据组的存储单元阵列和输出电路，在外部端子上以第一数据速率串行输出第一和第二数据组 。 在测试操作模式下，输出电路响应于控制信号以外部终端的第二数据速率输出第一数据组或第二数据组，而不切换测试模式。 第二数据速率可能低于第一数据速率。

公开(公告)号：US08243540B2

公开(公告)日：2012-08-14

申请号：US13137768

申请日：2011-09-12

Applicant: Hyong-yong Lee ,  Chan-sub Jun

Inventor： Hyong-yong Lee ,  Chan-sub Jun

IPC: G11C7/00

CPC classification number: G11C29/32 ,  G11C11/401 ,  G11C29/14

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

公开(公告)号：US20120014189A1

公开(公告)日：2012-01-19

申请号：US13137768

申请日：2011-09-12

Applicant: Hyong-yong Lee ,  Chan-sub Jun

Inventor： Hyong-yong Lee ,  Chan-sub Jun

IPC: G11C29/00

CPC classification number: G11C29/32 ,  G11C11/401 ,  G11C29/14

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

Abstract translation: 实施例公开半导体存储器件及其测试方法。 半导体存储器件包括在正常工作模式下以第一数据速率提供第一和第二数据组的存储单元阵列和输出电路，在外部端子上以第一数据速率串行输出第一和第二数据组 。 在测试操作模式下，输出电路响应于控制信号以外部终端的第二数据速率输出第一数据组或第二数据组，而不切换测试模式。 第二数据速率可能低于第一数据速率。

公开(公告)号：US08036052B2

公开(公告)日：2011-10-11

申请号：US12071552

申请日：2008-02-22

Applicant: Hyong-yong Lee ,  Chan-sub Jun

Inventor： Hyong-yong Lee ,  Chan-sub Jun

IPC: G11C7/00

CPC classification number: G11C29/32 ,  G11C11/401 ,  G11C29/14

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

Abstract translation: 实施例公开半导体存储器件及其测试方法。 半导体存储器件包括在正常工作模式下以第一数据速率提供第一和第二数据组的存储单元阵列和输出电路，在外部端子上以第一数据速率串行输出第一和第二数据组 。 在测试操作模式下，输出电路响应于控制信号以外部终端的第二数据速率输出第一数据组或第二数据组，而不切换测试模式。 第二数据速率可能低于第一数据速率。