公开(公告)号：US20150206560A1

公开(公告)日：2015-07-23

申请号：US14573379

申请日：2014-12-17

申请人： Hyun-Joon Kang ,  Yongchun Kim ,  Sungkook Shin

发明人： Hyun-Joon Kang ,  Yongchun Kim ,  Sungkook Shin

IPC分类号： G11C7/10 ,  G01R31/3193

CPC分类号： G11C29/023 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/222 ,  G11C29/022 ,  G11C29/028

摘要： A write leveling control method which includes registering data-related signal (DRS) reference delay values corresponding to types of memory modules in a leveling reference table; transmitting write leveling-related signals to a first type of memory module mounted on a target board; detecting timing skews between a clock signal and data-related signals received from memory devices on the mounted memory module; and adjusting a delay of a data-related signal transmitted to a memory device of the mounted memory module if a corresponding timing skew is outside of a first range, based on the DRS reference delay value corresponding to the mounted memory module.

摘要翻译： 一种写入调平控制方法，其包括在对准参考表中登记与存储器模块的类型对应的数据相关信号（DRS）参考延迟值; 将写平均相关信号发送到安装在目标板上的第一类型的存储器模块; 检测时钟信号与从所安装的存储器模块上的存储器件接收到的数据相关信号之间的时序偏差; 以及如果对应的定时偏移在第一范围之外，则基于与所安装的存储器模块对应的DRS参考延迟值，调整发送到所安装的存储器模块的存储器件的数据相关信号的延迟。