公开(公告)号：US07102446B1

公开(公告)日：2006-09-05

申请号：US11056995

申请日：2005-02-11

申请人： Hyung-Rok Lee ,  Moon-Sang Hwang ,  Sang-Hyun Lee ,  Bong-Joon Lee ,  Deog-Kyoon Jeong

发明人： Hyung-Rok Lee ,  Moon-Sang Hwang ,  Sang-Hyun Lee ,  Bong-Joon Lee ,  Deog-Kyoon Jeong

IPC分类号： H03L7/07 ,  H03L7/087 ,  H04B1/40 ,  H04B1/50

CPC分类号： H03L7/087 ,  H03K23/507 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/10 ,  H03L2207/06 ,  H04L7/0337 ,  Y10S331/02

摘要： A phase lock loop (PLL) for controlling a sampling clock or other clock, and a data sampling circuit, transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling the VCO by changing its frequency-voltage characteristic. The coarse control loop includes a frequency lock detector and voltage range monitoring logic. Typically, the frequency lock detector locks operation of the coarse control loop when the difference between the VCO output clock frequency and a reference frequency decreases to within a predetermined threshold, and the unlocked coarse control loop employs the voltage range monitoring logic to change the VCO frequency-voltage characteristic when the VCO's fine control voltage leaves a predetermined range. Other aspects are a transceiver (including at least two receiver interfaces and a transmitter interface) implementing a clocking scheme employing no more than three PLLs for clock generation, and a transceiver having a multi-layered receiver interface including digital circuitry and a single clock-generating PLL (an analog PLL for generating a multiphase clock to be shared by all layers of the receiver interface). Each receiver interface layer performs blind oversampling on a different received signal using the multiphase clock and the digital circuitry includes multilayered digital phase lock loop circuitry which receives the oversampled data.

摘要翻译： 用于控制采样时钟或其他时钟的锁相环（PLL）以及数据采样电路，收发器或包括这种PLL的其它装置。 PLL包括多范围VCO，用于控制VCO的至少一个精细控制环路和用于通过改变其频率 - 电压特性来控制VCO的粗略控制环路。 粗调控制回路包括一个频率锁定检测器和电压范围监控逻辑。 通常，当VCO输出时钟频率和参考频率之间的差减小到预定阈值时，频率锁定检测器锁定粗略控制环路的操作，而解锁的粗略控制环路采用电压范围监控逻辑来改变VCO频率 当VCO的精细控制电压离开预定范围时的电压特性。 其他方面是实现采用不超过三个PLL用于时钟产生的时钟方案的收发器（包括至少两个接收器接口和发射器接口），以及具有包括数字电路和单个时钟产生的多层接收器接口的收发器 PLL（用于产生要由接收器接口的所有层共享的多相时钟的模拟PLL）。 每个接收器接口层使用多相时钟在不同的接收信号上执行盲过采样，并且数字电路包括接收过采样数据的多层数字锁相环电路。