公开(公告)号：US20040225867A1

公开(公告)日：2004-11-11

申请号：US10773848

申请日：2004-02-05

Inventor： Alan B. Kyker ,  Per Hammarlund ,  Chan Lee ,  Robert F. Krick ,  Hitesh Ahuja ,  William Alexander ,  Joseph Rohlman

IPC: G06F009/40 ,  G06F009/44

CPC classification number: G06F9/30178 ,  G06F9/30156 ,  G06F9/3016 ,  G06F9/30167

Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

公开(公告)号：US20040210324A1

公开(公告)日：2004-10-21

申请号：US10827869

申请日：2004-04-20

Applicant: International Business Machines Corporation

Inventor： Kunikazu Yoda ,  Hiroyuki Okano

IPC: G06F015/00 ,  G05B011/01 ,  G06F009/40 ,  G06F009/30 ,  G06F019/00 ,  G05B013/02

CPC classification number: G05B5/01 ,  G05D23/1917

Abstract: For determination as to whether there is a possibility that temperature control satisfying conditions according to an upper limit LH_i and a lower limit LL_i of the annealing control temperatures of annealing object steel sections i will be realized under restrictions on limit values U and D of the control temperature increase and decrease rates, computation is performed without using dynamic programming requiring an enormous amount of data on a continuous annealing line of a steelwork. Annealing object steel sections in an annealing object steel band 12 to be computed are assigned numbers 1, 2, . . . , n in order from the first time division in the direction of movement. T_i is a time required to pass the annealing object steel section i through a predetermined point at which the steel section undergoes temperature control. LH_1nullLL_1nullb is given. X_inullnullIL_inullD*T_i, IH_inullU*T_inull is computed. When X_ L_i1 f, Y_inullX_i L_i. When X_i L_inullf, Y_inullX_i. Ynulli is computed from inull1 to inulln in ascending order.

Abstract translation: 为了确定是否存在满足根据退火对象钢部i的退火控制温度的退火控制温度的上限LH_i和下限LL_i的条件的温度控制的可能性，在对控制的限制值U和D的限制下实现 温度升高和降低率，在不使用需要在钢结构的连续退火线上大量数据的动态规划的情况下进行计算。 对要计算的退火对象钢带12中的退火对象钢部分分配号码1,2。 。 。 ，n按顺序从第一次划分的方向移动。 T_i是将退火对象钢部i通过钢部进行温度控制的规定点所需的时间。 LH_1 = LL_1 = b给出。 计算X_i = [IL_i-D * T_i，IH_i + U * T_i]。 当X_ L_i <1> f，Y_i = X_i L_i。 当X_i L_i = f，Y_i = X_i。 从i = 1到i = n以升序计算Y-i。

公开(公告)号：US20030159018A1

公开(公告)日：2003-08-21

申请号：US10081053

申请日：2002-02-21

Inventor： John Alan Miller ,  Michael J. St. Clair

IPC: G06F015/163 ,  G06F009/54 ,  G06F009/00 ,  G06F015/00 ,  G06F009/40 ,  G06F009/30

CPC classification number: G06F9/3806 ,  G06F9/30054

Abstract: An instruction pipeline in a microprocessor includes one or more of the pipelines maintaining a return buffer. Upon detecting a call instruction, a pipeline will push the return address onto its return buffer. The pipeline will then determine if the call instruction was detected by a second pipeline and will send the return address to the second pipeline if the call was not detected by the second pipeline. Upon detecting a return instruction, the pipeline will pop the return address at the top of its return buffer. The return address may then be used in the instruction pipeline. The pipeline will send a request to a third pipeline to fill its return buffer with entries from the third pipeline's return buffer. The pipeline will determine if the return instruction was detected by a second pipeline and will send the return address at the top of its return buffer to the second pipeline if the return was not detected by the second pipeline.

Abstract translation: 微处理器中的指令流水线包括保持返回缓冲器的一条或多条管道。 在检测到呼叫指令时，流水线将返回地址推送到其返回缓冲区。 然后，管道将确定呼叫指令是否被第二管道检测到，并且如果第二管道没有检测到呼叫，则将返回地址发送到第二管道。 检测到返回指令后，管道将弹出返回缓冲区顶部的返回地址。 然后可以在指令流水线中使用返回地址。 流水线将向第三条流水线发送请求，以从第三条流水线的返回缓冲区中输入条目来填充其返回缓冲区。 流水线将确定返回指令是否被第二个流水线检测到，并且如果第二个管道没有检测到返回，并且将其返回缓冲区顶部的返回地址发送到第二个管道。

公开(公告)号：US20030135711A1

公开(公告)日：2003-07-17

申请号：US10047809

申请日：2002-01-15

Applicant: INTEL CORPORATION

Inventor： Ken Shoemaker ,  Sailesh Kottapalli ,  Kin-Kee Sit

IPC: G06F015/00 ,  G06F009/40 ,  G06F009/30

CPC classification number: G06F9/3802 ,  G06F9/3851 ,  G06F9/3885

Abstract: An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second thread. A multi-thread scheduler coupled to the instruction fetch units and a execution unit. The multi-thread scheduler determines the width of the execution unit and the execution unit executes the threads accordingly.

公开(公告)号：US20030014613A1

公开(公告)日：2003-01-16

申请号：US09144302

申请日：1998-08-31

Inventor： NARESH H. SONI

IPC: G06F015/00 ,  G06F009/30 ,  G06F009/40

CPC classification number: G06F8/445 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

Abstract: A data processing system having a distributed reservation station is provided which stores basic blocks of code in the form of microprocessor instructions. The present invention is capable of distributing basic blocks of code to the various distributed reservation stations. Due to the smaller number of entries in the distributed reservation stations, the look up time required to find a particular instruction is much less than in a centralized reservation station. Additional instruction level parallelism is achieved by maintaining single basic blocks of code in the distributed reservation stations. This is because instructions which are grouped together are less likely to use the same resources, e.g. registers and memory locations, therefore, they will exhibit more data, control and resource independence. In contrast, when instructions are not associated with one another (e.g. in different basic blocks) they are more likely to use the same resources (execution units), data resources (registers) and be subject to control dependencies (branching), thus causing a greater chance of dependency that may cause instructions to have to wait for resources to become available. Also, with a distributed reservation station, an independent scheduler can be used for each one of the distributed reservation stations. When the instruction is ready for execution, the scheduler will remove that instruction from the distributed reservation station and queue that instruction(s) for immediate execution at the particular execution unit. Multiple independent schedulers will provide greater efficiency when compared to a single scheduler which must contend with approximately 20-24 instructions that have increased dependency on one another.

Abstract translation: 提供具有分布式预留站的数据处理系统，其以微处理器指令的形式存储基本的代码块。 本发明能够将基本的代码块分配给各种分布式预留站。 由于分布式预留站中的条目数量较少，所以查找特定指令所需的查找时间远小于集中式预留站。 通过在分布式保留站中维护单个基本代码块来实现附加指令级并行性。 这是因为分组在一起的指令不太可能使用相同的资源，例如 寄存器和存储器位置，因此它们将展现更多的数据，控制和资源独立性。 相比之下，当指令彼此不相关（例如，在不同的基本块中）时，它们更有可能使用相同的资源（执行单元），数据资源（寄存器）并受到控制依赖性（分支）的约束，从而导致 更大的依赖机会可能导致指令必须等待资源变得可用。 此外，利用分布式预留站，可以为分布式预留站中的每一个使用独立的调度器。 当指令准备执行时，调度程序将从分布式预留站中删除该指令，并排队该指令，以便在特定执行单元立即执行。 与单个调度器相比，多个独立的调度程序将提供更高的效率，该调度程序必须与大约20-24个指令之间的相互依赖性增加。

公开(公告)号：US20020199082A1

公开(公告)日：2002-12-26

申请号：US10172977

申请日：2002-06-18

Applicant: Applied Materials, Inc.

Inventor： Arulkumar P. Shanmugasundram ,  Helen Armer ,  Alexander T. Schwarm

IPC: G06F009/30 ,  G06F009/40

CPC classification number: B24B53/017 ,  B24B37/042 ,  B24B49/03 ,  B24B49/18 ,  G05B19/00 ,  G05B19/19 ,  G05B19/41865 ,  G05B2219/32053 ,  G05B2219/32065 ,  G05B2219/45031 ,  H01L21/31053 ,  H01L21/67253 ,  H01L21/67276 ,  H01L22/20 ,  Y02P90/14 ,  Y02P90/18 ,  Y02P90/20

Abstract: The invention relates to a method, system and computer program useful for producing a product, such as a microelectronic device, for example in an assembly line, where the production facility includes parallel production of assembly lines of products on identically configured chambers, tools and/or modules. Control is provided between such chambers. Behaviors of a batch of wafers (or of each wafer) are collected as the first batch (or each wafer) is processed by one of the identically configured chambers in one assembly line to produce the microelectronic device. The information relating to the behavior is shared with a controller of another one (or more) of the identically configured chambers, process tools and/or modules, to provide an adjustment of the process tool and thereby to produce a second batch (or next wafer) which is substantially identical, within tolerance, to the first batch (or wafer).

Abstract translation: 本发明涉及用于生产例如在装配线中的微电子装置的产品的方法，系统和计算机程序，其中生产设备包括在相同配置的室，工具和/ 或模块。 在这些室之间提供控制。 一批晶片（或每个晶片）的行为被收集，因为第一批（或每个晶片）由一个组装线中的相同配置的腔室中的一个处理，以产生微电子器件。 与行为相关的信息与另一个（或多个）相同配置的腔室，过程工具和/或模块的控制器共享，以提供过程工具的调整，从而产生第二批次（或下一个晶片 ），其在公差范围内与第一批（或晶片）基本相同。

公开(公告)号：US20030208673A1

公开(公告)日：2003-11-06

申请号：US09761326

申请日：2001-01-16

Inventor： Shailender Chaudhry ,  Marc Tremblay

IPC: G06F009/30 ,  G06F009/40 ,  G06F015/00

CPC classification number: G06F9/3851 ,  G06F9/3842

Abstract: One embodiment of the present invention provides a system that facilitates entering and exiting a critical section of code for a speculative thread. The system supports a head thread that executes program instructions, and the speculative thread that speculatively executes program instructions in advance of the head thread. During an entry into the critical section by the speculative thread, the system increments a variable containing a number of virtual locks held by the speculative thread. Note that a virtual lock held by the speculative thread is associated with the critical section and is used to keep track of the fact that the speculative thread has entered the critical section. Also note that this virtual lock does not prevent the speculative thread or other threads from entering the critical section. During an exit from the critical section by the speculative thread, the system decrements the variable containing the number of virtual locks held by the speculative thread. The speculative eventually receives a request to perform a join operation with the head thread to merge state associated with the speculative thread into state associated with the head thread. Upon receiving this request, the speculative thread waits to perform the join operation until the variable containing the number of virtual locks held by the speculative thread equals zero. In one embodiment of the present invention, the system additionally waits to perform the join operation until no virtual locks in a list of virtual locks accessed by the speculative thread are held by the other head threads.

Abstract translation: 本发明的一个实施例提供一种便于进入和退出用于推测线程的关键代码段的系统。 该系统支持执行程序指令的头部线程，以及在头部线程之前推测性地执行程序指令的推测线程。 在通过推测线程进入关键部分期间，系统会增加包含推测线程所持有的多个虚拟锁的变量。 请注意，由推测线程保持的虚拟锁与关键部分相关联，并用于跟踪推测线程已进入关键部分的事实。 还要注意，这个虚拟锁并不能阻止投机线程或其他线程进入临界区。 在通过推测线程从关键部分退出之前，系统递减包含推测线程所持有的虚拟锁数的变量。 推测最终接收到执行与头线程的连接操作的请求，以将与推测线程相关联的状态合并到与头线程相关联的状态。 在接收到该请求之后，推测线程等待执行连接操作，直到包含推测线程所持有的虚拟锁数的变量等于零为止。 在本发明的一个实施例中，系统另外等待执行连接操作，直到由推测线程访问的虚拟锁列表中的虚拟锁由其他头部线程保持为止。

公开(公告)号：US20030208672A1

公开(公告)日：2003-11-06

申请号：US09683383

申请日：2001-12-20

Applicant: IBM

Inventor： Jens Leenstra ,  Antje Mueller ,  Juergen Pille ,  Dieter Wendel

IPC: G06F009/30 ,  G06F009/40 ,  G06F015/00

CPC classification number: G06F9/3873 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

Abstract: A method and system for operating a high frequency outprocessor with increased pipeline length. A new scheme is disclosed to reduce the pipeline by the detection and exploitation of so called nullno_dependencynull for an instruction. A nullno dependencynull signal tells that all required source data is available for the instruction at least one cycle before the source data valid bit(s) are inserted into the issue queue. Therefore, one or more stages of the pipeline are bypassed. Bypassing the pipeline stages for this nullno dependencynull conditions is especially important since a no dependency is found when the queue is empty. Furthermore, this bypass is very effective when the queue is relatively empty. Therefore, introducing such a bypass reduces effectively the performance drawback of a longer pipeline.

Abstract translation: 一种用于操作具有增加的管道长度的高频外部处理器的方法和系统。 公开了一种新方案，通过对指令的所谓“不相关”的检测和利用来减少流水线。 “无依赖”信号指示在将源数据有效位插入到发出队列之前至少一个周期，所有必需的源数据可用于该指令。 因此，管道的一个或多个阶段被绕过。 绕过这个“不依赖”条件的流水线阶段特别重要，因为当队列为空时，找不到依赖关系。 此外，当队列相对空时，此旁路是非常有效的。 因此，引入这样的旁路有效地降低了更长管道的性能缺陷。

公开(公告)号：US20030120897A1

公开(公告)日：2003-06-26

申请号：US10032177

申请日：2001-12-21

Inventor： Michael Steven Schlansker

IPC: G06F015/00 ,  G06F009/40 ,  G06F009/30

CPC classification number: G06F9/321 ,  G06F9/3853 ,  G06F9/3885

Abstract: A multiprocessor data processing system for executing a program having branch instructions therein, each branch instruction specifying a target address in the program defining an instruction that is to be executed if that branch instruction causes the program to branch. The data processing system includes a plurality of processing sections having a function unit, a local memory, and a pointer. The local memory stores instruction sequences from the program that is to be executed by the function unit in that processing section. The pointer contains a value defining the next instruction in the local memory to be executed by the function unit. The pointers in each of the processing sections are reset to a new value determined by the target address of one of the branch instructions when a function unit branches in response to that branch instruction.

Abstract translation: 一种用于执行其中具有分支指令的程序的多处理器数据处理系统，每个分支指令在所述程序中指定所述程序中的目标地址，所述程序定义如果所述分支指令导致所述程序分支则要执行的指令。 数据处理系统包括具有功能单元，本地存储器和指针的多个处理部分。 本地存储器存储要由该处理部分中的功能单元执行的程序的指令序列。 该指针包含定义要由功能单元执行的本地存储器中的下一个指令的值。 当功能单元响应于该分支指令而分支时，每个处理部分中的指针被重置为由一个分支指令的目标地址确定的新值。

公开(公告)号：US20030023835A1

公开(公告)日：2003-01-30

申请号：US10251508

申请日：2002-09-20

Inventor： Stavros Kalafatis ,  Alan B. Kyker ,  Robert D. Fisch

IPC: G06F015/00 ,  G06F009/40 ,  G06F009/30

CPC classification number: G06F9/3802 ,  G06F9/3808 ,  G06F9/3844 ,  G06F9/3851

Abstract: A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The predetermined quantity of the instruction information may be equal to or greater than a minimum quantity of instruction information for a full instruction of a first instruction set.

Abstract translation: 一种在多线程处理器内执行线程切换操作的方法，包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。 响应于对第一线程的第一预定量的指令信息的调度的检测，针对指令流缓冲器的输出执行线程切换操作。 因此开始从指令流缓存器发送第二线程的指令信息。 指令信息的预定量可以等于或大于用于第一指令集的完整指令的指令信息的最小量。