公开(公告)号：US3863232A

公开(公告)日：1975-01-28

申请号：US42830073

申请日：1973-12-26

Applicant: IBM

Inventor： JOHNSON DARREL D ,  KAUFMAN CARL L ,  LOHREY FRED H ,  ROBBINS GORDON J

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04

Abstract: An associative array of memory cells is arranged with its read cells interleaved with its storage cells to reduce the physical space required by the array. Two rows of read cells have four rows of storage cells on each side thereof except that the uppermost row of the read cells in the array has only two rows of the storage cells thereabove and the lowermost row of the read cells in the array has only two rows of the storage cells therebelow. One half of the read cells in each row of the read cells provides an output for one of the two adjacent rows of the storage cells.

Abstract translation: 布置存储器单元的关联阵列，其读取单元与其存储单元交错以减少阵列所需的物理空间。 两行读单元格在其每一侧上具有四行存储单元，除了阵列中的读单元的最上一行仅具有上述存储单元的两行之外，阵列中的读单元的最下排只有两行 行存储单元的行。 读单元的每一行中读取单元的一半为存储单元的两个相邻行之一提供输出。