公开(公告)号：US3643231A

公开(公告)日：1972-02-15

申请号：US3643231D

申请日：1970-04-20

Applicant: IBM

Inventor： LOHREY FRED H ,  WIEDMANN SIEGFRIED K

IPC: G11C15/04 ,  G11C11/40 ,  H03K3/286

CPC classification number: G11C15/04 ,  Y10S148/037 ,  Y10S148/085

Abstract: This specification discloses an associative memory storage cell having two cross-connected transistors with the word line for the cell connected to the common emitters of the two transistors and having each of the bases of the two transistors connected to the base of an input/output transistor. This emitter of each of these input/output transistors is connected to a separate bit line and the collectors of the input/output transistors are connected together and to the associative sense amplifier. To associatively search the memory, one of the bit lines is lowered. This causes the input/output transistor connected to the lowered bit line to conduct and thereby give a no-match signal to the associative sense amplifier if its base is connected to the base of the conducting one of the two cross-connected transistors and it causes that transistor to remain nonconductive and thereby give a match signal to the associative sense amplifier if it is connected to the base of the nonconducting one of the two crossconnected transistors.

Abstract translation: 本说明书公开了一种具有两个交叉连接晶体管的相关存储器存储单元，该晶体管具有用于连接到两个晶体管的公共发射极的单元的单元线，并且两个晶体管的每个基极连接到输入/输出晶体管的基极 。 这些输入/输出晶体管中的每一个的该发射极连接到单独的位线，并且输入/输出晶体管的集电极连接在一起并连接到关联读出放大器。 为了联合搜索存储器，其中一个位线被降低。 这导致连接到降低的位线的输入/输出晶体管导通，从而如果其基极连接到两个交叉连接的晶体管中的导通的基极的基极，则向相关读出放大器提供不匹配信号，并且导致 该晶体管保持不导通，从而如果连接到两个交叉连接的晶体管中的不导通的晶体管的基极，则向相关读出放大器提供匹配信号。

公开(公告)号：US3863232A

公开(公告)日：1975-01-28

申请号：US42830073

申请日：1973-12-26

Applicant: IBM

Inventor： JOHNSON DARREL D ,  KAUFMAN CARL L ,  LOHREY FRED H ,  ROBBINS GORDON J

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04

Abstract: An associative array of memory cells is arranged with its read cells interleaved with its storage cells to reduce the physical space required by the array. Two rows of read cells have four rows of storage cells on each side thereof except that the uppermost row of the read cells in the array has only two rows of the storage cells thereabove and the lowermost row of the read cells in the array has only two rows of the storage cells therebelow. One half of the read cells in each row of the read cells provides an output for one of the two adjacent rows of the storage cells.

Abstract translation: 布置存储器单元的关联阵列，其读取单元与其存储单元交错以减少阵列所需的物理空间。 两行读单元格在其每一侧上具有四行存储单元，除了阵列中的读单元的最上一行仅具有上述存储单元的两行之外，阵列中的读单元的最下排只有两行 行存储单元的行。 读单元的每一行中读取单元的一半为存储单元的两个相邻行之一提供输出。