公开(公告)号：US3877051A

公开(公告)日：1975-04-08

申请号：US29872972

申请日：1972-10-18

Applicant: IBM

Inventor： CALHOUN HARRY C ,  FREED LARRY E ,  KAUFMAN CARL L

IPC: H01L21/00 ,  H01L23/485 ,  H01L23/522 ,  H01L19/00

CPC classification number: H01L23/485 ,  H01L21/00 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S438/98 ,  H01L2924/00

Abstract: A planar semiconductor integrated circuit chip structure containing a planar surface from which a plurality of regions of different types and concentrations of conductivity-determining impurities extends into the chip to provide the active and passive devices of the circuit. The surface is passivated with an insulative structure containing at least two layers with a metallization pattern for interconnecting the integrated circuit devices formed on the first layer and via holes passing through the second or upper layer into contact with various portions of this metallization pattern. The via holes are arranged so that a majority of the holes are disposed above surface regions having such impurity types and concentrations that would form Schottky barrier contacts with the metal of contacts formed in said via holes. Accordingly, if during the formation of the via holes by etching through the second layer, there is an attendant further etching through the first layer to the surface of a semiconductor region, said region will form a Schottky barrier contact with the metal deposited in the via holes, which contact will act to prevent a short circuit between the metallization and the surface region.

Abstract translation: 一种平面半导体集成电路芯片结构，其包含不同类型和多个导电性确定杂质的多个区域从该平面表面延伸到芯片中以提供该电路的有源和无源器件。 表面被绝缘结构钝化，其中包含至少两层的金属化图案，用于将形成在第一层上的集成电路器件和穿过第二层或上层的通孔与该金属化图案的各个部分接触。 通孔布置成使得大部分孔布置在具有这样的杂质类型和浓度的表面区域上方，该杂质类型和浓度将与形成在所述通孔中的触点的金属形成肖特基势垒接触。 因此，如果在通过蚀刻通过第二层形成通路孔期间，伴随着进一步的蚀刻通过第一层到半导体区域的表面，所述区域将与沉积在通孔中的金属形成肖特基势垒接触 该接触件将起作用以防止金属化和表面区域之间的短路。

公开(公告)号：US3863232A

公开(公告)日：1975-01-28

申请号：US42830073

申请日：1973-12-26

Applicant: IBM

Inventor： JOHNSON DARREL D ,  KAUFMAN CARL L ,  LOHREY FRED H ,  ROBBINS GORDON J

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04

Abstract: An associative array of memory cells is arranged with its read cells interleaved with its storage cells to reduce the physical space required by the array. Two rows of read cells have four rows of storage cells on each side thereof except that the uppermost row of the read cells in the array has only two rows of the storage cells thereabove and the lowermost row of the read cells in the array has only two rows of the storage cells therebelow. One half of the read cells in each row of the read cells provides an output for one of the two adjacent rows of the storage cells.

Abstract translation: 布置存储器单元的关联阵列，其读取单元与其存储单元交错以减少阵列所需的物理空间。 两行读单元格在其每一侧上具有四行存储单元，除了阵列中的读单元的最上一行仅具有上述存储单元的两行之外，阵列中的读单元的最下排只有两行 行存储单元的行。 读单元的每一行中读取单元的一半为存储单元的两个相邻行之一提供输出。