公开(公告)号：US3868723A

公开(公告)日：1975-02-25

申请号：US42426773

申请日：1973-12-13

Applicant: IBM

Inventor： LECHATON JOHN S ,  RICHARD LEO P ,  SMITH DARYL C

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/06 ,  H01L29/49 ,  H01L11/00 ,  H01L15/00

CPC classification number: H01L29/4966 ,  H01L21/76819 ,  H01L23/5226 ,  H01L29/0638 ,  H01L29/495 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method of partially planarizing an electrically insulative layer over an integrated circuit substrate which has a raised line metallization pattern having narrower lines and wider lines. The insulative layer has narrower and wider elevations corresponding to the underlying lines. Resputtering of said insulative layer is conducted for an amount of time sufficient to planarize the narrower elevations in the layer but insufficient to so planarize its wider elevations. This method is useful in planarizing insulative layer elevations through which via holes are to be formed, particularly via holes which are wider than the underlying metallizing lines which they contact. Such a planarization method in via hole formation avoids the tunneling effects which would otherwise result from the over-chemical etching necessary to form the via holes.

Abstract translation: 一种在集成电路基板上部分平坦化电绝缘层的方法，所述集成电路基板具有具有窄线和宽线的凸起线金属化图案。 绝缘层具有对应于底层线的较窄和较宽的高度。 进行所述绝缘层的再溅射一段时间，足以平坦化层中较窄的高度，但不足以平坦化其较高的高度。 该方法可用于平坦化通过其形成通孔的绝缘层高度，特别是通孔比它们接触的下面的金属化线更宽。 通孔形成中的这种平面化方法避免了由形成通孔所必需的过度化学蚀刻而导致的隧道效应。