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    Binary batch adder utilizing threshold counters
    3.
    发明授权
    Binary batch adder utilizing threshold counters 失效
    二进制批量添加器使用阈值计数器

    公开(公告)号：US3603776A

    公开(公告)日：1971-09-07

    申请号：US3603776D

    申请日：1969-01-15

    Applicant: IBM

    Inventor： WEINBERGER ARNOLD

    IPC: G06F7/50 ,  G06F7/509 ,  G06F7/60 ,  G06F5/02

    CPC classification number: G06F7/509 ,  G06F7/607 ,  G06F2207/4818

    Abstract: Disclosed are counters for counting inputs in terms of a fewer number of outputs. The counters are useful in batch adders for simultaneously adding a plurality of multibit numbers. The counters include first and second binary threshold function generators which each receive a different group of inputs. The generators are in parallel with respect to the inputs and each generates a plurality of binary threshold functions. The binary threshold functions are selectively combined in first, second and third threshold combining circuits to form the counter outputs. The combining circuits are placed in parallel and each circuit logically combines one or more threshold function inputs derived from the function generators.

    Partitioning logic operations in a generalized matrix system
    4.
    发明授权
    Partitioning logic operations in a generalized matrix system 失效
    在一般化矩阵系统中分割逻辑运算

    公开(公告)号：US3593317A

    公开(公告)日：1971-07-13

    申请号：US3593317D

    申请日：1969-12-30

    Applicant: IBM

    Inventor： FLEISHER HAROLD ,  WEINBERGER ARNOLD ,  WINKLER VAUGHN D

    IPC: H03K19/177 ,  G06C15/00

    CPC classification number: H03K19/177

    Abstract: An improved method and means to implement a logic function F of N variables by partitioning the logic operation in a plurality of generalized logic matrices. It is first mathematically demonstrated that a function F of N variables may be expanded into subfunctions of a lesser number of variables. These subfunctions may be logically implemented individually and then logically combined so as to produce the desired function of N variables with a concomitant savings in logic circuitry over that required if the functions were directly implemented. The means used to implement the logic function F are a plurality of generalized logic matrices, each of which comprises a plurality of logic gates arranged in columns and rows, an input decoder for accepting the input variables, and a storage register for varying the functions generated at the output of the matrix. These matrices are arranged in cascade so that, as the function F is constructed from the several subfunctions, additional variables are inserted at each matrix stage until the function F of N variables is fully generated.

    Hybrid associative memory
    5.
    发明授权
    Hybrid associative memory 失效
    混合相关记忆

    公开(公告)号：US3644906A

    公开(公告)日：1972-02-22

    申请号：US3644906D

    申请日：1969-12-24

    Applicant: IBM

    Inventor： WEINBERGER ARNOLD

    IPC: G11C15/00 ,  G06F15/78 ,  G06F17/30 ,  G11C15/04 ,  G11C5/02

    CPC classification number: G06F17/30982 ,  G06F15/7839

    Abstract: A memory is disclosed in which words are located by both associative and nonassociative addressing. The nonassociative portion of the address defines a general category for the word being searched and a corresponding portion of the memory. The associative portion of the address is searched within the addressed portion of the memory without regard to the actual memory location. Conventional nonassociative storage cell arrays are arranged to be addressed as an associative memory of threestate storage cells.

    Improved decimal adder for directly implementing bcd addition utilizing logic circuitry
    6.
    发明授权
    Improved decimal adder for directly implementing bcd addition utilizing logic circuitry 失效
    改进的十进制添加剂，用于直接实施使用逻辑电路的BCD添加

    公开(公告)号：US3629565A

    公开(公告)日：1971-12-21

    申请号：US3629565D

    申请日：1970-02-13

    Applicant: IBM

    Inventor： SCHMOOKLER MARTIN S ,  WEINBERGER ARNOLD

    IPC: G06F7/494 ,  G06F7/50

    CPC classification number: G06F7/494 ,  G06F2207/4924

    Abstract: An improved method and logic system for adding two decimal numbers which are coded in a four-bit binary form. The method includes generating a propagate carry signal Pi for each of the four bits which is the OR function of the bit inputs, generating a generate carry signal Gi for each of the four bits which is the AND function of the bit inputs, and generating a binary carry C1 for the first bit. The decimal carry for the addition is then generated by a novel carry look-ahead technique by employing these signals: Pi, Gi, and the binary carry C1. The binary coded decimal bit signals representative of the decimal sum are also generated directly from these signals and, hence, the adder differs from prior art decimal adders which first performed binary addition in each bit and then added 6 to these binary sums whenever a decimal carry occurred so as to produce corrected binary signals representative of the coded decimal number. Several systems are disclosed employing this method and include a four-logic level, two-digit decimal adder, a three-logic level, two-digit decimal adder; and a six-logic level, eight-digit decimal adder. The six-logic level, eight-digit decimal adder combines concepts of the disclosed novel method for implementing decimal carries, as well as conventional group carry techniques used in parallel binary adders.

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