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    Improved decimal adder for directly implementing bcd addition utilizing logic circuitry
    2.
    发明授权
    Improved decimal adder for directly implementing bcd addition utilizing logic circuitry 失效
    改进的十进制添加剂，用于直接实施使用逻辑电路的BCD添加

    公开(公告)号：US3629565A

    公开(公告)日：1971-12-21

    申请号：US3629565D

    申请日：1970-02-13

    Applicant: IBM

    Inventor： SCHMOOKLER MARTIN S ,  WEINBERGER ARNOLD

    IPC: G06F7/494 ,  G06F7/50

    CPC classification number: G06F7/494 ,  G06F2207/4924

    Abstract: An improved method and logic system for adding two decimal numbers which are coded in a four-bit binary form. The method includes generating a propagate carry signal Pi for each of the four bits which is the OR function of the bit inputs, generating a generate carry signal Gi for each of the four bits which is the AND function of the bit inputs, and generating a binary carry C1 for the first bit. The decimal carry for the addition is then generated by a novel carry look-ahead technique by employing these signals: Pi, Gi, and the binary carry C1. The binary coded decimal bit signals representative of the decimal sum are also generated directly from these signals and, hence, the adder differs from prior art decimal adders which first performed binary addition in each bit and then added 6 to these binary sums whenever a decimal carry occurred so as to produce corrected binary signals representative of the coded decimal number. Several systems are disclosed employing this method and include a four-logic level, two-digit decimal adder, a three-logic level, two-digit decimal adder; and a six-logic level, eight-digit decimal adder. The six-logic level, eight-digit decimal adder combines concepts of the disclosed novel method for implementing decimal carries, as well as conventional group carry techniques used in parallel binary adders.

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