公开(公告)号：US20230178478A1

公开(公告)日：2023-06-08

申请号：US17991351

申请日：2022-11-21

Applicant: IMEC VZW

Inventor： Gaspard HIBLOT ,  Douglas Charles LA TULIPE ,  Anne JOURDAIN

IPC: H01L23/522 ,  H01L23/48 ,  H01L21/02 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L23/5226 ,  H01L21/02019 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827

Abstract: A method producing a nano-sized interconnect structure that electrically connects the front side of a semiconductor substrate to the back side of the substrate is provided. In one aspect, the method produces a semiconductor component such as an integrated circuit chip that includes active devices formed on the front side of the substrate, and an interconnect network such as a power delivery network on the back side of the substrate. The substrate includes a lower semiconductor layer, an intermediate layer, and an upper layer. A trench is formed through the upper layer, the material of the intermediate layer is etched from inside the trench to form a cavity at the foot of the trench, and the trench and the cavity are filled with an electrically conductive material to form a buried rail with a wide contact pad at the foot of the rail, that is, wider than the width of the rail and extending between the front and back surfaces of the intermediate layer. A nanoTSV connection is processed from the back of the substrate, the nanoTSV contacting the contact pad, to thereby form the interconnect structure.