公开(公告)号：US12188895B2

公开(公告)日：2025-01-07

申请号：US17692717

申请日：2022-03-11

Applicant: IMEC VZW

Inventor： David Barge ,  Bert Du Bois ,  Simone Severi ,  Ashesh Ray Chaudhuri

IPC: H01L21/00 ,  G01N27/414

Abstract: A method for forming a nanopore transistor and a nanopore transistor is provided. The method includes: (a) forming an aperture in a filler material by: (i) providing a fin comprising a semiconductor layer and a top layer; (ii) patterning the top layer to form a pillar; (iii) embedding the pillar in a filler material; (iv) removing the pillar, leaving an aperture; (v) lining the aperture with a spacer material; (b) forming a nanopore by etching through the aperture; (b) lining the nanopore with a dielectric, (c) forming a source and a drain by either: between steps a.ii and a.iii, doping the bottom semiconductor layer by using the pillar as a mask, or after step c, filling the aperture with a sealing material, thereby forming a post; removing the filler material; doping the bottom semiconductor layer by using the post as a mask; and removing the sealing material.

公开(公告)号：US20230127645A1

公开(公告)日：2023-04-27

申请号：US18045287

申请日：2022-10-10

Applicant: IMEC VZW

Inventor： Simone Severi ,  Bert Du Bois ,  Ashesh Ray Chaudhuri

IPC: B81C1/00 ,  B81B1/00

Abstract: An intermediate structure for a microfluidic device and a method for manufacturing a microfluidic device are provided. The method includes: a) providing a first substrate having a first layer thereon, and a second layer on the first layer; b) forming a first nanopore in the second layer, in such a way that a part of the first layer coincides with a bottom of the first nanopore; c) exposing said part of the first layer to a liquid etchant, thereby forming a cavity under the first nanopore, the cavity having a larger width than a width of the bottom of the first nanopore; d) filling the first nanopore and the cavity with a filling material, thereby forming a first plug; e) forming a bottom fluidic access for the nanopore by removing part of the first substrate and part of the first layer so as to expose the plug; and f) removing the plug, thereby fluidly connecting the bottom fluidic access to the nanopore.

公开(公告)号：US20220334079A1

公开(公告)日：2022-10-20

申请号：US17692717

申请日：2022-03-11

Applicant: IMEC VZW

Inventor： David Barge ,  Bert Du Bois ,  Simone Severi ,  Ashesh Ray Chaudhuri

IPC: G01N27/414

Abstract: A method for forming a nanopore transistor and a nanopore transistor is provided. The method includes: (a) forming an aperture in a filler material by: (i) providing a fin comprising a semiconductor layer and a top layer; (ii) pattering the top layer to form a pillar; (iii) embedding the pillar in a filler material; (iv) removing the pillar, leaving an aperture; (v) lining the aperture with a spacer material; (b) forming a nanopore by etching through the aperture; (b) lining the nanopore with a dielectric, (c) forming a source and a drain by either: between steps a.ii and a.iii, doping the bottom semiconductor layer by using the pillar as a mask, or after step c, filling the aperture with a sealing material, thereby forming a post; removing the filler material; doping the bottom semiconductor layer by using the post as a mask; and removing the sealing material.