公开(公告)号：US12188895B2

公开(公告)日：2025-01-07

申请号：US17692717

申请日：2022-03-11

Applicant: IMEC VZW

Inventor： David Barge ,  Bert Du Bois ,  Simone Severi ,  Ashesh Ray Chaudhuri

IPC: H01L21/00 ,  G01N27/414

Abstract: A method for forming a nanopore transistor and a nanopore transistor is provided. The method includes: (a) forming an aperture in a filler material by: (i) providing a fin comprising a semiconductor layer and a top layer; (ii) patterning the top layer to form a pillar; (iii) embedding the pillar in a filler material; (iv) removing the pillar, leaving an aperture; (v) lining the aperture with a spacer material; (b) forming a nanopore by etching through the aperture; (b) lining the nanopore with a dielectric, (c) forming a source and a drain by either: between steps a.ii and a.iii, doping the bottom semiconductor layer by using the pillar as a mask, or after step c, filling the aperture with a sealing material, thereby forming a post; removing the filler material; doping the bottom semiconductor layer by using the post as a mask; and removing the sealing material.

公开(公告)号：US20220334079A1

公开(公告)日：2022-10-20

申请号：US17692717

申请日：2022-03-11

Applicant: IMEC VZW

Inventor： David Barge ,  Bert Du Bois ,  Simone Severi ,  Ashesh Ray Chaudhuri

IPC: G01N27/414

Abstract: A method for forming a nanopore transistor and a nanopore transistor is provided. The method includes: (a) forming an aperture in a filler material by: (i) providing a fin comprising a semiconductor layer and a top layer; (ii) pattering the top layer to form a pillar; (iii) embedding the pillar in a filler material; (iv) removing the pillar, leaving an aperture; (v) lining the aperture with a spacer material; (b) forming a nanopore by etching through the aperture; (b) lining the nanopore with a dielectric, (c) forming a source and a drain by either: between steps a.ii and a.iii, doping the bottom semiconductor layer by using the pillar as a mask, or after step c, filling the aperture with a sealing material, thereby forming a post; removing the filler material; doping the bottom semiconductor layer by using the post as a mask; and removing the sealing material.

公开(公告)号：US10267733B2

公开(公告)日：2019-04-23

申请号：US15312116

申请日：2015-05-22

Applicant: IMEC VZW

Inventor： Pol Van Dorpe ,  Liesbet Lagae ,  Peter Peumans ,  Andim Stassen ,  Philippe Helin ,  Bert Du Bois ,  Simone Severi

IPC: G01N21/64 ,  G01N21/77

Abstract: The present disclosure relates to semiconductor devices for detecting fluorescent particles. At least one embodiment relates to an integrated semiconductor device for detecting fluorescent tags. The device includes a first layer, a second layer, a third layer, a fourth layer, and a fifth layer. The first layer includes a detector element. The second layer includes a rejection filter. The third layer is fabricated from dielectric material. The fourth layer is an optical waveguide configured and positioned such that a top surface of the fourth layer is illuminated with an evanescent tail of excitation light guided by the optical waveguide when the fluorescent tags are present. The fifth layer includes a microfluidic channel. The optical waveguide is configured and positioned such that the microfluidic channel is illuminated with the evanescent tail. The detector element is positioned such that light from activated fluorescent tags can be received.

公开(公告)号：US20170082544A1

公开(公告)日：2017-03-23

申请号：US15312116

申请日：2015-05-22

Applicant: IMEC VZW

Inventor： Pol Van Dorpe ,  Liesbet Lagae ,  Peter Peumans ,  Andim Stassen ,  Philippe Helin ,  Bert Du Bois ,  Simone Severi

IPC: G01N21/64

CPC classification number: G01N21/6428 ,  G01N21/6454 ,  G01N21/648 ,  G01N21/7703 ,  G01N2201/0873

Abstract: The present disclosure relates to semiconductor devices for detecting fluorescent particles. At least one embodiment relates to an integrated semiconductor device for detecting fluorescent tags. The device includes a first layer, a second layer, a third layer, a fourth layer, and a fifth layer. The first layer includes a detector element. The second layer includes a rejection filter. The third layer is fabricated from dielectric material. The fourth layer is an optical waveguide configured and positioned such that a top surface of the fourth layer is illuminated with an evanescent tail of excitation light guided by the optical waveguide when the fluorescent tags are present. The fifth layer includes a microfluidic channel. The optical waveguide is configured and positioned such that the microfluidic channel is illuminated with the evanescent tail. The detector element is positioned such that light from activated fluorescent tags can be received.

公开(公告)号：US20250110080A1

公开(公告)日：2025-04-03

申请号：US18979912

申请日：2024-12-13

Applicant: IMEC VZW

Inventor： David Barge ,  Bert Du Bois ,  Simone Severi ,  Ashesh Ray Chaudhuri

IPC: G01N27/414

Abstract: A method for forming a nanopore transistor and a nanopore transistor is provided. The method includes: (a) forming an aperture in a filler material by: (i) providing a fin comprising a semiconductor layer and a top layer; (ii) pattering the top layer to form a pillar; (iii) embedding the pillar in a filler material; (iv) removing the pillar, leaving an aperture; (v) lining the aperture with a spacer material; (b) forming a nanopore by etching through the aperture; (b) lining the nanopore with a dielectric, (c) forming a source and a drain by either: between steps a.ii and a.iii, doping the bottom semiconductor layer by using the pillar as a mask, or after step c, filling the aperture with a sealing material, thereby forming a post; removing the filler material; doping the bottom semiconductor layer by using the post as a mask; and removing the sealing material.

公开(公告)号：US20230127645A1

公开(公告)日：2023-04-27

申请号：US18045287

申请日：2022-10-10

Applicant: IMEC VZW

Inventor： Simone Severi ,  Bert Du Bois ,  Ashesh Ray Chaudhuri

IPC: B81C1/00 ,  B81B1/00

Abstract: An intermediate structure for a microfluidic device and a method for manufacturing a microfluidic device are provided. The method includes: a) providing a first substrate having a first layer thereon, and a second layer on the first layer; b) forming a first nanopore in the second layer, in such a way that a part of the first layer coincides with a bottom of the first nanopore; c) exposing said part of the first layer to a liquid etchant, thereby forming a cavity under the first nanopore, the cavity having a larger width than a width of the bottom of the first nanopore; d) filling the first nanopore and the cavity with a filling material, thereby forming a first plug; e) forming a bottom fluidic access for the nanopore by removing part of the first substrate and part of the first layer so as to expose the plug; and f) removing the plug, thereby fluidly connecting the bottom fluidic access to the nanopore.