公开(公告)号：US20250029872A1

公开(公告)日：2025-01-23

申请号：US18762318

申请日：2024-07-02

Applicant: IMEC VZW

Inventor： Anshul Gupta ,  Zsolt Tokei ,  Stefan Decoster ,  Gayle Murdoch ,  Seongho Park

IPC: H01L21/768 ,  H01L23/522

Abstract: Methods and systems for producing an interconnect via are provided. A conductive layer is produced on a substrate having an upper surface of a dielectric material with conductors or contacts embedded in the dielectric material. A dielectric layer is produced on the conductive layer. An opening is formed in the dielectric layer and filled with a conductive material to form a conductive via. The dielectric layer and the via are planarized to a common planar level. At least one hardmask line which overlaps the via is formed. The dielectric material and the conductive material of the via and of the conductive layer are removed in the areas not covered by the hardmask line, resulting in a conductive line having an interconnect via on its top surface. The interconnect via is aligned to the width of the conductive line. The hardmask line is removed and a planar dielectric surface is produced.