公开(公告)号：US20210193512A1

公开(公告)日：2021-06-24

申请号：US17081337

申请日：2020-10-27

Applicant: IMEC VZW

Inventor： Martin O'Toole ,  Zsolt Tokei ,  Christopher Wilson ,  Stefan Decoster

IPC: H01L21/768 ,  H01L23/538 ,  H01L21/033

Abstract: A method is provided for producing electrically conductive lines (23a, 23b), wherein spacers are deposited on a sacrificial structure present on a stack of layers, including a hardmask layer on top of a dielectric layer into which the lines are to be embedded, and an intermediate layer on top of the hardmask layer. A self-aligned litho-etch step is then performed to create an opening in the intermediate layer, the opening being self-aligned to the space between two adjacent sidewalls of the sacrificial structure. This self-aligned step precedes the deposition of spacers on the sacrificial structure, so that spacers are also formed on the transverse sidewalls of the opening, i.e. perpendicular to the spacers on the walls of the sacrificial structure. A blocking material is provided in the area of the bottom of the opening that is surrounded on all sides by spacers, thereby creating a block with a reduced size.

公开(公告)号：US20240170328A1

公开(公告)日：2024-05-23

申请号：US18514461

申请日：2023-11-20

Applicant: IMEC VZW

Inventor： Anshul Gupta ,  Zsolt Tokei ,  Stefan Decoster

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76877

Abstract: A method includes forming and patterning a first dielectric over a substrate; covering the first dielectric with metal and planarizing the metal exposing a surface of the first dielectric and forming a first metal; forming a second dielectric over the first dielectric and the first metal; covering the second dielectric with metal and planarizing the metal exposing a surface of the second dielectric and forming a second metal; forming a mask over the second dielectric and the second metal; and transferring: a first sub-pattern of the mask into a first portion of the first metal to form a lower metal, a second sub-pattern of the mask into a first portion of the second metal and a second portion of the first metal to form a stacked metal, and a third sub-pattern of the mask into a second portion of the second metal to form an upper metal.

公开(公告)号：US20230170300A1

公开(公告)日：2023-06-01

申请号：US18053636

申请日：2022-11-08

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Stefan Decoster

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/76885 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76877

Abstract: A method for forming an interconnection structure for a semiconductor device and an interconnection structure is disclosed. The method includes forming a conductive layer on an insulating layer and etching the conductive layer to form a first conductive line. Thereafter, a spacer is formed on a side wall of a first end portion of the first conductive line. The method further includes forming a second conductive line, parallel to the first conductive line, having a second end portion, wherein a side wall of the second end portion is arranged to abut the spacer such that the first and the second metal line are extending along the same line and separated by the spacer. A recess is formed in the second metal line, extending along a portion of the second metal line, and a second mask layer is arranged in the recess.

公开(公告)号：US11264271B2

公开(公告)日：2022-03-01

申请号：US17081337

申请日：2020-10-27

Applicant: IMEC VZW

Inventor： Martin O'Toole ,  Zsolt Tokei ,  Christopher Wilson ,  Stefan Decoster

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/538

Abstract: A method is provided for producing electrically conductive lines (23a, 23b), wherein spacers are deposited on a sacrificial structure present on a stack of layers, including a hardmask layer on top of a dielectric layer into which the lines are to be embedded, and an intermediate layer on top of the hardmask layer. A self-aligned litho-etch step is then performed to create an opening in the intermediate layer, the opening being self-aligned to the space between two adjacent sidewalls of the sacrificial structure. This self-aligned step precedes the deposition of spacers on the sacrificial structure, so that spacers are also formed on the transverse sidewalls of the opening, i.e. perpendicular to the spacers on the walls of the sacrificial structure. A blocking material is provided in the area of the bottom of the opening that is surrounded on all sides by spacers, thereby creating a block with a reduced size.

公开(公告)号：US20250029872A1

公开(公告)日：2025-01-23

申请号：US18762318

申请日：2024-07-02

Applicant: IMEC VZW

Inventor： Anshul Gupta ,  Zsolt Tokei ,  Stefan Decoster ,  Gayle Murdoch ,  Seongho Park

IPC: H01L21/768 ,  H01L23/522

Abstract: Methods and systems for producing an interconnect via are provided. A conductive layer is produced on a substrate having an upper surface of a dielectric material with conductors or contacts embedded in the dielectric material. A dielectric layer is produced on the conductive layer. An opening is formed in the dielectric layer and filled with a conductive material to form a conductive via. The dielectric layer and the via are planarized to a common planar level. At least one hardmask line which overlaps the via is formed. The dielectric material and the conductive material of the via and of the conductive layer are removed in the areas not covered by the hardmask line, resulting in a conductive line having an interconnect via on its top surface. The interconnect via is aligned to the width of the conductive line. The hardmask line is removed and a planar dielectric surface is produced.

公开(公告)号：US20230170255A1

公开(公告)日：2023-06-01

申请号：US17833223

申请日：2022-06-06

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Stefan Decoster

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/3213

CPC classification number: H01L21/76897 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53252 ,  H01L21/76837 ,  H01L21/32139

Abstract: A method for forming an interconnection structure (10) for a semiconductor device is disclosed, wherein a first conductive layer is etched to form a set of third conductive lines (113) above a first and second conductive line (101, 108). At least one of the third conductive lines comprises a contacting portion forming a first via connection (114) to the second conductive line. The method further comprises forming spacers (115) on side walls of the set of third conductive lines, and forming, between two neighboring spacers, a via hole (116) extending to the underlying first conductive line. A second conductive layer is deposited, filling the via hole to form a second via connection (118) and forming a set of fourth conductive lines (119) extending between the spacers.