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22 条记录 (耗时 0.015 秒)

    FORMING VIAS IN A SEMICONDUCTOR DEVICE
    1.
    发明申请
    FORMING VIAS IN A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210313217A1

    公开(公告)日：2021-10-07

    申请号：US17223876

    申请日：2021-04-06

    申请人： Tokyo Electron Limited ,  IMEC VZW

    发明人： Kaushik Kumar ,  Yannick Feurprier ,  Zsolt Tokei

    IPC分类号： H01L21/768

    摘要： In certain embodiments, a method includes forming a first etch stop layer on a first metallization layer of a semiconductor substrate. The method further includes forming, prior to forming a second metallization layer over the first metallization layer, an opening in the first etch stop layer according to a supervia mask. The method further includes forming the second metallization layer over the first metallization layer and forming a second etch stop layer on the second metallization layer. The method further includes forming, prior to forming a third metallization layer over the second metallization layer, an opening in the second etch stop layer according to the supervia mask. The method further includes forming the third metallization layer over the second metallization layer and etching a supervia opening from the third metallization layer to the first metallization layer according to the supervia mask.

    METHOD OF FORMING A MULTI-LEVEL INTERCONNECT STRUCTURE IN A SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD OF FORMING A MULTI-LEVEL INTERCONNECT STRUCTURE IN A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210028106A1

    公开(公告)日：2021-01-28

    申请号：US16936271

    申请日：2020-07-22

    申请人： IMEC vzw

    发明人： Basoene Briggs ,  Vladimir Machkaoutsan ,  Zsolt Tokei

    IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

    摘要： A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.

    METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN BODY
    3.
    发明公开
    METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN BODY 审中-公开

    公开(公告)号：US20240234207A9

    公开(公告)日：2024-07-11

    申请号：US18486370

    申请日：2023-10-13

    申请人： IMEC VZW

    发明人： Boon Teik Chan ,  Hans Mertens ,  Zsolt Tokei ,  Naoto Horiguchi

    IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L29/40

    CPC分类号： H01L21/76879 ,  H01L21/76802 ,  H01L23/5286 ,  H01L29/401

    摘要： A method provided for interconnecting a buried wiring line and a source/drain body. The method includes: forming a fin structure on a substrate, the fin structure comprising at least one channel layer; forming a buried wiring line in a trench extending alongside the fin structure, wherein the buried wiring line is capped by a first insulating layer structure; forming a source/drain body on the at least one channel layer by epitaxy; forming a via hole in the first insulating layer structure to expose an upper surface of the buried wiring line; forming a metal via in the via hole; forming a second insulating layer structure over the first insulating layer structure, wherein a contact opening is defined in the second insulating layer structure to expose the source/drain body and an upper via portion of the metal via; and forming a source/drain contact in the contact opening, on the upper via portion and the source/drain body, thereby inter-connecting the buried wiring line and the source/drain body.

    Semiconductor fabrication method for producing nano-scaled electrically conductive lines
    4.
    发明授权
    Semiconductor fabrication method for producing nano-scaled electrically conductive lines 有权

    公开(公告)号：US11264271B2

    公开(公告)日：2022-03-01

    申请号：US17081337

    申请日：2020-10-27

    申请人： IMEC VZW

    发明人： Martin O'Toole ,  Zsolt Tokei ,  Christopher Wilson ,  Stefan Decoster

    IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L23/538

    摘要： A method is provided for producing electrically conductive lines (23a, 23b), wherein spacers are deposited on a sacrificial structure present on a stack of layers, including a hardmask layer on top of a dielectric layer into which the lines are to be embedded, and an intermediate layer on top of the hardmask layer. A self-aligned litho-etch step is then performed to create an opening in the intermediate layer, the opening being self-aligned to the space between two adjacent sidewalls of the sacrificial structure. This self-aligned step precedes the deposition of spacers on the sacrificial structure, so that spacers are also formed on the transverse sidewalls of the opening, i.e. perpendicular to the spacers on the walls of the sacrificial structure. A blocking material is provided in the area of the bottom of the opening that is surrounded on all sides by spacers, thereby creating a block with a reduced size.

    Apex angle reduction in a LED device with a LED array
    5.
    发明授权
    Apex angle reduction in a LED device with a LED array 有权

    公开(公告)号：US11005016B2

    公开(公告)日：2021-05-11

    申请号：US16706002

    申请日：2019-12-06

    申请人： IMEC VZW

    发明人： Soeren Steudel ,  Zsolt Tokei ,  Paul Heremans

    IPC分类号： H01L33/58 ,  H01L27/15 ,  H01L33/62

    摘要： A Light Emitting Diode (LED) device, particularly a micro-LED (μLED) device, suitable for a μLED display is described. The LED device comprises a LED array with a plurality of LEDs 12. It also comprises at least one top contact and bottom contact electrically connected to the LED array. Further, it comprises a conductive structure arranged above the LED array and the top contact, respectively, and electrically connected to the top contact. The conductive structure is, regarding each LED of the LED array, configured to absorb a first part of the light emitted by the LED, and to pass a second part of the light emitted by the LED. An emission angle (beam angle) of the passed light is thereby smaller than an emission angle of the light emitted by the LED.

    METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN BODY
    7.
    发明公开
    METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN BODY 审中-公开

    公开(公告)号：US20240136225A1

    公开(公告)日：2024-04-25

    申请号：US18486370

    申请日：2023-10-12

    申请人： IMEC VZW

    发明人： Boon Teik Chan ,  Hans Mertens ,  Zsolt Tokei ,  Naoto Horiguchi

    IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L29/40

    CPC分类号： H01L21/76879 ,  H01L21/76802 ,  H01L23/5286 ,  H01L29/401

    摘要： A method provided for interconnecting a buried wiring line and a source/drain body. The method includes: forming a fin structure on a substrate, the fin structure comprising at least one channel layer; forming a buried wiring line in a trench extending alongside the fin structure, wherein the buried wiring line is capped by a first insulating layer structure; forming a source/drain body on the at least one channel layer by epitaxy; forming a via hole in the first insulating layer structure to expose an upper surface of the buried wiring line; forming a metal via in the via hole; forming a second insulating layer structure over the first insulating layer structure, wherein a contact opening is defined in the second insulating layer structure to expose the source/drain body and an upper via portion of the metal via; and forming a source/drain contact in the contact opening, on the upper via portion and the source/drain body, thereby inter-connecting the buried wiring line and the source/drain body.

    Method of forming a multi-level interconnect structure in a semiconductor device
    9.
    发明授权
    Method of forming a multi-level interconnect structure in a semiconductor device 有权

    公开(公告)号：US11088070B2

    公开(公告)日：2021-08-10

    申请号：US16936271

    申请日：2020-07-22

    申请人： IMEC vzw

    发明人： Basoene Briggs ,  Vladimir Machkaoutsan ,  Zsolt Tokei

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    摘要： A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.

    Semiconductor Fabrication Method for Producing Nano-Scaled Electrically Conductive Lines
    10.
    发明申请
    Semiconductor Fabrication Method for Producing Nano-Scaled Electrically Conductive Lines 有权

    公开(公告)号：US20210193512A1

    公开(公告)日：2021-06-24

    申请号：US17081337

    申请日：2020-10-27

    申请人： IMEC VZW

    发明人： Martin O'Toole ,  Zsolt Tokei ,  Christopher Wilson ,  Stefan Decoster

    IPC分类号： H01L21/768 ,  H01L23/538 ,  H01L21/033

    摘要： A method is provided for producing electrically conductive lines (23a, 23b), wherein spacers are deposited on a sacrificial structure present on a stack of layers, including a hardmask layer on top of a dielectric layer into which the lines are to be embedded, and an intermediate layer on top of the hardmask layer. A self-aligned litho-etch step is then performed to create an opening in the intermediate layer, the opening being self-aligned to the space between two adjacent sidewalls of the sacrificial structure. This self-aligned step precedes the deposition of spacers on the sacrificial structure, so that spacers are also formed on the transverse sidewalls of the opening, i.e. perpendicular to the spacers on the walls of the sacrificial structure. A blocking material is provided in the area of the bottom of the opening that is surrounded on all sides by spacers, thereby creating a block with a reduced size.