公开(公告)号：US20250120088A1

公开(公告)日：2025-04-10

申请号：US18906994

申请日：2024-10-04

Applicant: IMEC VZW

Inventor： Sana Rachidi ,  Maarten Rosmeulen ,  Silvia Armini

IPC: H10B43/35 ,  H10B43/10 ,  H10B43/27

Abstract: The present disclosure relates to a method that includes forming a layer stack over a substrate; forming first recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back inter-gate spacer layers of the layer stack; forming sacrificial layers in the first recessed areas; forming second recessed areas in the sidewall by laterally etching back gate layers of the layer stack; forming a lateral memory stack in each second recessed area by selectively depositing, in the second recessed areas, a blocking oxide and, subsequently, a charge trap material. The method further includes removing the sacrificial layers by etching from the memory hole; re-growing the inter-gate spacer layers such that the lateral memory stacks are vertically separated by the re-grown inter-gate spacer layers; forming a tunneling oxide layer in the memory hole; and forming a channel layer along the tunneling oxide layer.

公开(公告)号：US20250118547A1

公开(公告)日：2025-04-10

申请号：US18906944

申请日：2024-10-04

Applicant: IMEC VZW

Inventor： Sana Rachidi ,  Geert Van den Bosch ,  Maarten Rosmeulen ,  Silvia Armini

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/764 ,  H01L21/768

Abstract: According to an aspect, a method of forming a memory structure for a 3D NAND flash memory includes forming a layer stack over a substrate, forming first recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back gate layers of the layer stack from the memory hole, and forming a lateral memory stack in each first recessed areas, by depositing a blocking oxide and, subsequently, a charge trap material. The method also includes forming second recessed areas in the sidewall by laterally etching back the inter-gate spacer layers from the memory hole and forming dummy layers in the second recessed areas. The method also includes lining the sidewall of the memory hole with a liner layer, subjecting the dummy layers to a thermal treatment process adapted to convert each dummy layer into an air gap structure, and forming a tunneling oxide layer in the memory hole, along the liner layer, and a channel layer along the tunneling oxide layer.