公开(公告)号：US20220005862A1

公开(公告)日：2022-01-06

申请号：US17366843

申请日：2021-07-02

Applicant: IMEC VZW

Inventor： Yunlong Li ,  Stefano Guerrieri ,  Ming Mao ,  Luis Moreno Hagelsieb

IPC: H01L27/146

Abstract: A method for forming a pixelated optoelectronic stack comprises forming a stacked layer structure that comprises a bottom electrode layer, an optoelectronic layer over the bottom electrode layer, and a patterned hard-mask comprising a pattern over the optoelectronic layer. The method comprises replicating the pattern into the optoelectronic layer and the bottom electrode layer, thereby forming a first intermediate pixelated stack comprising at least two islands of stack separated from one another by stack-free areas; providing an electrically insulating layer on the first intermediate pixelated stack; removing a top portion of the electrically insulating layer and removing any remaining hard-mask so that a top surface of the electrically insulating layer is coplanar with an exposed top surface of the first intermediate pixelated stack, yielding a second intermediate pixelated stack; and forming a top transparent electrode layer over the second intermediate pixelated stack.

公开(公告)号：US11929385B2

公开(公告)日：2024-03-12

申请号：US17366843

申请日：2021-07-02

Applicant: IMEC VZW

Inventor： Yunlong Li ,  Stefano Guerrieri ,  Ming Mao ,  Luis Moreno Hagelsieb

IPC: H01L27/146

CPC classification number: H01L27/14689 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14643

Abstract: A method for forming a pixelated optoelectronic stack comprises forming a stacked layer structure that comprises a bottom electrode layer, an optoelectronic layer over the bottom electrode layer, and a patterned hard-mask comprising a pattern over the optoelectronic layer. The method comprises replicating the pattern into the optoelectronic layer and the bottom electrode layer, thereby forming a first intermediate pixelated stack comprising at least two islands of stack separated from one another by stack-free areas; providing an electrically insulating layer on the first intermediate pixelated stack; removing a top portion of the electrically insulating layer and removing any remaining hard-mask so that a top surface of the electrically insulating layer is coplanar with an exposed top surface of the first intermediate pixelated stack, yielding a second intermediate pixelated stack; and forming a top transparent electrode layer over the second intermediate pixelated stack.

公开(公告)号：US11282702B2

公开(公告)日：2022-03-22

申请号：US17068785

申请日：2020-10-12

Applicant: IMEC VZW ,  KATHOLIEKE UNIVERSITEIT LEUVEN

Inventor： Philippe Soussan ,  Vasyl Motsnyi ,  Luc Haspeslagh ,  Stefano Guerrieri ,  Olga Syshchyk ,  Bernardette Kunert ,  Robert Langer

IPC: H01L27/00 ,  H01L21/02 ,  H01L29/66

Abstract: The present invent provides a method comprising forming a first wafer comprising a first substrate of a group IV semiconductor, and a group III-V semiconductor device structure formed by selective area epitaxial growth on a surface portion of a front side of the first substrate. The method further comprises forming a second wafer comprising a second substrate of a group IV semiconductor, and a group IV semiconductor device structure formed on a front side of the second substrate, and bonding the first wafer to the second wafer with the front side of the first substrate facing the front side of the second wafer.