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    PMOS transistor including low thermal-budget gate stack
    1.
    发明授权
    PMOS transistor including low thermal-budget gate stack 有权

    公开(公告)号：US11282837B2

    公开(公告)日：2022-03-22

    申请号：US16688776

    申请日：2019-11-19

    Applicant: IMEC vzw

    Inventor： Jacopo Franco ,  Hiroaki Arimura ,  Benjamin Kaczer

    IPC: H01L21/02 ,  H01L23/367 ,  H01L27/092 ,  H01L29/00 ,  H01L21/8238 ,  H01L29/51

    Abstract: A p-channel metal-oxide-semiconductor (pMOS) transistor including a gate stack which includes: a silicon oxide comprising dielectric interlayer on a substrate, wherein the dielectric interlayer has a thickness below 1 nm; a high-k dielectric layer having a higher dielectric constant compared to the dielectric interlayer; a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer and in direct contact with the dielectric interlayer, for shifting down a high-K bandgap of the high-k dielectric layer with relation to a valence band of the substrate, where the first dipole-forming capping layer has a thickness below 2 nm; at least one work function metal above the high-k dielectric layer. Advantageously, the pMOS transistor includes low negative bias temperature instability (NBTI) and therefore high reliability without the use of a reliability anneal which makes the pMOS transistor suitable for use as back end of line (BEOL) devices.

    PMOS TRANSISTOR INCLUDING LOW THERMAL-BUDGET GATE STACK
    2.
    发明申请
    PMOS TRANSISTOR INCLUDING LOW THERMAL-BUDGET GATE STACK 审中-公开

    公开(公告)号：US20200176446A1

    公开(公告)日：2020-06-04

    申请号：US16688776

    申请日：2019-11-19

    Applicant: IMEC vzw

    Inventor： Jacopo Franco ,  Hiroaki Arimura ,  Benjamin Kaczer

    IPC: H01L27/092 ,  H01L23/367 ,  H01L21/8238 ,  H01L21/02

    Abstract: A p-channel metal-oxide-semiconductor (pMOS) transistor including a gate stack which includes: a silicon oxide comprising dielectric interlayer on a substrate, wherein the dielectric interlayer has a thickness below lnm; a high-k dielectric layer having a higher dielectric constant compared to the dielectric interlayer; a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer and in direct contact with the dielectric interlayer, for shifting down a high-K bandgap of the high-k dielectric layer with relation to a valence band of the substrate, where the first dipole-forming capping layer has a thickness below 2nm; at least one work function metal above the high-k dielectric layer. Advantageously, the pMOS transistor includes low negative bias temperature instability (NBTI) and therefore high reliability without the use of a reliability anneal which makes the pMOS transistor suitable for use as back end of line (BEOL) devices.

    COMPLEXITY-REDUCED SIMULATION OF CIRCUIT RELIABILITY
    4.
    发明申请
    COMPLEXITY-REDUCED SIMULATION OF CIRCUIT RELIABILITY 审中-公开
    电路可靠性的复杂减少仿真

    公开(公告)号：US20160283629A1

    公开(公告)日：2016-09-29

    申请号：US15081635

    申请日：2016-03-25

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

    Inventor： Pieter Weckx ,  Dmitrios Rodopoulos ,  Benjamin Kaczer ,  Francky Catthoor

    IPC: G06F17/50

    CPC classification number: G06F17/5036 ,  G06F2217/76 ,  G06F2217/80 ,  G06F2217/82

    Abstract: A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.

    Abstract translation: 公开了一种用于模拟电子电路的系统和方法。 该方法包括创建从n维参数空间内选择的电路或设备参数点的有限集合。 该方法包括针对该组的每个电路或设备参数点确定性能度量的对应响应值和相应的发生概率。 该方法包括针对性能度量的预定值确定总出现概率。

    COMPLEXITY-REDUCED SIMULATION OF CIRCUIT RELIABILITY
    6.
    发明申请
    COMPLEXITY-REDUCED SIMULATION OF CIRCUIT RELIABILITY 审中-公开

    公开(公告)号：US20200089829A1

    公开(公告)日：2020-03-19

    申请号：US16522555

    申请日：2019-07-25

    Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

    Inventor： Pieter Weckx ,  Dmitrios Rodopoulos ,  Benjamin Kaczer ,  Francky Catthoor

    IPC: G06F17/50

    Abstract: A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.

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