Phase-lock loop
    1.
    发明授权

    公开(公告)号:US09608645B2

    公开(公告)日:2017-03-28

    申请号:US14257796

    申请日:2014-04-21

    CPC classification number: H03L7/095 H03L7/0995 H03L7/113 H03L7/18 Y10S331/02

    Abstract: In one implementation an output signal of an oscillator is varied to be within a desired frequency band with respect to a reference signal, the output signal having a plurality of phases. The implementation may include comparing the output signal with the reference signal, counting falling edges about each phase of the number of phases in a predetermined time period and summing to define a count output; comparing the count output with a product of the number of phases of the output signal and the factor to define a comparison, generating a control signal based upon the comparison, and inputting the control signal to the oscillator to alter the output signal thereof.

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