公开(公告)号：US20030081475A1

公开(公告)日：2003-05-01

申请号：US10315342

申请日：2002-12-10

Applicant: Infineon Technologies AG

Inventor： Werner Weber ,  Roland Thewes

IPC: G11C007/00

CPC classification number: G11C11/16 ,  G11C11/1673

Abstract: A description is given of a method and a circuit configuration for evaluating an information content of a memory cell, preferably of an MRAM memory cell, or of a memory cell array. In order to be able to perform accurate and reliable evaluation of the memory cell, a first current value flowing through the memory cell or a voltage value correlated with the current value is measured and conducted through a first circuit branch, which has a switch and a capacitance, and is buffer-stored. The memory cell is subsequently subjected to a programming operation. Afterward, in the same memory cell a second current value or voltage value is measured and conducted through a second circuit branch that has a switch and a capacitance and is buffer-stored there. The two measured values are compared with one another in an evaluation unit.

Abstract translation: 给出了用于评估存储单元（优选地是MRAM存储单元）或存储单元阵列的信息内容的方法和电路配置的描述。 为了能够对存储单元进行准确可靠的评估，流过该存储单元的第一电流值或与电流值相关的电压值被测量并通过第一电路支路进行传输，第一电路支路具有开关和 电容，并被缓冲存储。 随后对存储单元进行编程操作。 之后，在相同的存储单元中，通过具有开关和电容的第二电路支路来测量并传导第二电流值或电压值，并将其缓冲存储在那里。 两个测量值在评估单元中相互比较。

公开(公告)号：US20010036102A1

公开(公告)日：2001-11-01

申请号：US09801715

申请日：2001-03-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Alexander Frey ,  Werner Weber ,  Till Schlosser

IPC: G11C011/24

CPC classification number: H01L27/10882 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10885 ,  H01L27/10897

Abstract: A DRAM memory (50) having a number of DRAM memory cells (51) is described, the memory cells (51) in each case having a storage capacitor (52) and a selection transistor (12) which are formed in the area of an at least essentially rectangular cell area (59), the cell areas (59) having a greater extent in the longitudinal direction (L) than in the width direction (B) and which are wired or can be wired to the cell periphery via a word line (56, 57) and a bit line (55). The word lines (56, 57) and the bit line (55) are conducted over the memory cells (51) and are at least essentially oriented perpendicularly to one another. To achieve, with increasing miniaturization of the DRAM memory patterns, during the transition from so-called nullfoldednull bit line architectures to so-called nullopennull bit line architectures that the bit line grid, and thus also the grid of corresponding read/write amplifiers, varies linearly in scale with the longitudinal extent (L) of the memory cells (51), it is provided according to the invention that the bit lines (55) are now oriented perpendicularly to the longitudinal extent (L) of the memory cells (51) in the direction of the lateral extent (B) of the memory cells (51)

Abstract translation: 描述了具有多个DRAM存储单元（51）的DRAM存储器（50），每个情况下的存储单元（51）具有存储电容器（52）和选择晶体管（12） 至少基本上矩形的单元区域（59），所述单元区域（59）在纵向方向（L）上比在宽度方向（B）上具有更大的程度，并且它们被布线或可以经由字连接到单元周边 线（56,57）和位线（55）。 字线（56,57）和位线（55）在存储器单元（51）上传导，并且至少基本上彼此垂直定向。 为了实现随着DRAM存储器模式的小型化，在从所谓的“折叠”位线结构转变到所谓的“开放”位线架构，即位线格栅，从而也是对应读/ 写放大器随着存储器单元（51）的纵向延伸（L）而在尺度上线性变化，根据本发明，提供了位线（55）垂直于存储器的纵向延伸（L）定向 在存储单元（51）的横向范围（B）的方向上的单元（51）