公开(公告)号：US09911693B2

公开(公告)日：2018-03-06

申请号：US14838768

申请日：2015-08-28

申请人： Micron Technology, Inc.

发明人： William R. Brown ,  Jenna L. Russon ,  Tim H. Bossart ,  Brian R. Watson ,  Nikolay A. Mirin ,  David A. Kewley

IPC分类号： H01L23/528 ,  H01L27/108 ,  H01L21/768 ,  H01L27/11582

CPC分类号： H01L23/528 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5283 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/11582 ,  H01L28/00

摘要： A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on the each of the first conductive lines is on the enlarged portion thereof.

公开(公告)号：US09768148B2

公开(公告)日：2017-09-19

申请号：US14588183

申请日：2014-12-31

申请人： Intel Corporation

发明人： Pete Vogt ,  Andre Schaefer ,  Warren Morrow ,  John Halbert ,  Jin Kim ,  Kenneth Shoemaker

IPC分类号： G11C5/06 ,  H01L25/065 ,  H01L27/108 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L25/0657 ,  G11C5/06 ,  H01L23/481 ,  H01L24/16 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

摘要： A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

公开(公告)号：US09754945B2

公开(公告)日：2017-09-05

申请号：US14452762

申请日：2014-08-06

申请人： GLOBALFOUNDRIES INC.

发明人： Eduard A. Cartier ,  Herbert L. Ho ,  Donghun Kang

IPC分类号： H01L27/108 ,  H01L49/02 ,  H01L29/92

CPC分类号： H01L27/1087 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10882 ,  H01L28/91

摘要： A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.

公开(公告)号：US20160322450A1

公开(公告)日：2016-11-03

申请号：US15139882

申请日：2016-04-27

申请人： Samsung Display Co., Ltd.

发明人： Ji-Eun Lee ,  Sun-Ja Kwon

IPC分类号： H01L27/32 ,  G09G3/3275 ,  G09G3/3266 ,  G09G3/3258 ,  G09G3/3233

CPC分类号： H01L51/0545 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2300/0866 ,  H01L27/10882 ,  H01L27/1285 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L51/107 ,  H01L51/5296

摘要： An organic light-emitting diode display is disclosed. In one aspect, the display includes a substrate, a scan line formed over the substrate and configured to provide a scan signal, and a data line crossing the scan line and configured to provide a data voltage. A driving voltage line crosses the scan line and is configured to provide a driving voltage. The display also includes a switching transistor electrically connected to the scan line and the data line and a driving transistor electrically connected to the switching transistor and including a driving gate electrode, a driving source electrode, and a driving drain electrode. The display further includes a storage capacitor including a first storage electrode formed over the driving transistor and the driving gate electrode as a second storage electrode. The second storage electrode overlaps the first storage electrode in the depth dimension and extends from the driving voltage line.

摘要翻译： 公开了一种有机发光二极管显示器。 一方面，显示器包括衬底，形成在衬底上并被配置为提供扫描信号的扫描线，以及跨越扫描线并被配置为提供数据电压的数据线。 驱动电压线穿过扫描线并被配置成提供驱动电压。 该显示器还包括电连接到扫描线和数据线的开关晶体管和与开关晶体管电连接并包括驱动栅电极，驱动源电极和驱动漏电极的驱动晶体管。 该显示器还包括一个存储电容器，该存储电容器包括形成在驱动晶体管上的第一存储电极和作为第二存储电极的驱动栅电极。 第二存储电极在深度尺寸上与第一存储电极重叠，并从驱动电压线延伸。

公开(公告)号：US09337201B2

公开(公告)日：2016-05-10

申请号：US13612507

申请日：2012-09-12

申请人： Lars Heineck ,  Jaydip Guha

发明人： Lars Heineck ,  Jaydip Guha

IPC分类号： H01L27/088 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10888

摘要： A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions. The inner source/drain region has opposing laterally outer sides. One of a pair of data/sense lines is electrically coupled to and against one of the outer sides of the inner source/drain region. The other of the pair of data/sense lines is electrically coupled to and against the other of the outer sides of the inner source/drain region. An access gate line is elevationally outward of the pair of electrically coupled data/sense lines and is operatively adjacent the channel region. A charge storage device is electrically coupled to the outer source/drain region. Other embodiments and additional aspects, including methods, are disclosed.

公开(公告)号：US09129896B2

公开(公告)日：2015-09-08

申请号：US13591065

申请日：2012-08-21

申请人： Yongjun Jeff Hu ,  Allen McTeer

发明人： Yongjun Jeff Hu ,  Allen McTeer

IPC分类号： H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L27/108

CPC分类号： H01L27/10805 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2656 ,  H01L23/528 ,  H01L27/088 ,  H01L27/10873 ,  H01L27/10882 ,  H01L29/167 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： An array includes vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The data/sense line has silicon-comprising semiconductor material between the transistors in that column that is conductively-doped n-type with at least one of As and Sb. The conductively-doped semiconductor material of the data/sense line includes a conductivity-neutral dopant between the transistors in that column. Methods are disclosed.

摘要翻译： 阵列包括垂直取向的晶体管，访问线的行和数据/感测线的列。 这些行的单独包括在该行中互连晶体管的访问线。 列的单独包括在该列中互连晶体管的数据/感测线。 数据/检测线在该列中的晶体管之间具有含硅的半导体材料，该导体掺杂n型与As和Sb中的至少一种导电掺杂。 数据/检测线的导电掺杂半导体材料包括该列中的晶体管之间的导电中性掺杂剂。 公开了方法。

公开(公告)号：US09012326B2

公开(公告)日：2015-04-21

申请号：US13087208

申请日：2011-04-14

申请人： Nam-Gun Kim ,  Yoonjae Kim ,  Sungil Cho

发明人： Nam-Gun Kim ,  Yoonjae Kim ,  Sungil Cho

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L27/108 ,  H01L27/22 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L27/102 ,  H01L27/115 ,  H01L27/24 ,  H01L45/00

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L27/1021 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/224 ,  H01L27/24 ,  H01L27/2409 ,  H01L28/91 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785 ,  H01L45/04 ,  H01L45/06 ,  H01L45/10 ,  H01L45/141 ,  H01L45/145

摘要： A lower layer of a microelectronic device may be patterned by forming a first sacrificial layer on the lower layer; patterning a plurality of spaced apart trenches in the first sacrificial layer; forming a second sacrificial layer in the plurality of spaced apart trenches; patterning the second sacrificial layer in the plurality of spaced apart trenches to define upper openings in the plurality of spaced apart trenches; and patterning the lower layer using the first and second sacrificial layers as a mask to form lower openings in the lower layer.

摘要翻译： 可以通过在下层上形成第一牺牲层来图案化微电子器件的下层; 在所述第一牺牲层中图形化多个间隔开的沟槽; 在所述多个间隔开的沟槽中形成第二牺牲层; 在所述多个间隔开的沟槽中图案化所述第二牺牲层以限定所述多个间隔开的沟槽中的上部开口; 并且使用第一和第二牺牲层作为掩模来图案化下层，以在下层中形成下部开口。

公开(公告)号：US08952436B2

公开(公告)日：2015-02-10

申请号：US13522862

申请日：2011-01-20

申请人： Sébastien Cremer ,  Frédérìc Lalanne ,  Marc Vernet

发明人： Sébastien Cremer ,  Frédérìc Lalanne ,  Marc Vernet

IPC分类号： H01L27/108 ,  H01L23/48 ,  H01L21/00 ,  G11C11/404 ,  G11C11/4094 ,  H01L27/02 ,  H01L49/02 ,  H01L23/522

CPC分类号： H01L27/10882 ,  G11C11/404 ,  G11C11/4094 ,  H01L23/5223 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A DRAM memory device includes at least one memory cell including a transistor having a first electrode, a second electrode and a control electrode. A capacitor is coupled to the first electrode. At least one electrically conductive line is coupled to the second electrode and at least one second electrically conductive line is coupled to the control electrode. The electrically conductive lines are located between the transistor and the capacitor. The capacitor can be provided above a fifth metal level.

摘要翻译： DRAM存储器件包括至少一个包括具有第一电极，第二电极和控制电极的晶体管的存储单元。 电容器耦合到第一电极。 至少一个导电线耦合到第二电极，并且至少一个第二导电线耦合到控制电极。 导电线位于晶体管和电容器之间。 电容器可以设置在第五金属层以上。

公开(公告)号：US08941163B2

公开(公告)日：2015-01-27

申请号：US13916240

申请日：2013-06-12

申请人： Renesas Electronics Corporation

发明人： Ichirou Mizuguchi ,  Hiroshi Furuta

IPC分类号： H01L27/108

CPC分类号： H01L27/10805 ,  H01L27/10811 ,  H01L27/10847 ,  H01L27/10882

摘要： A DRAM device includes plural N-channel MIS transistors arranged in a matrix over a P well, and a plurality of capacitors formed corresponding to the plurality of N-channel MIS transistors, and plural word lines formed corresponding to each row of the plurality of N-channel MIS transistors, and a plurality of bit lines formed corresponding to each column of the plurality of N-channel MIS transistors, and a P+ diffusion layer formed extending in the direction that the plurality of word lines extend and supplied with a p well voltage potential.

摘要翻译： DRAM装置包括在P阱上以矩阵形式布置的多个N沟道MIS晶体管和对应于多个N沟道MIS晶体管形成的多个电容器，并且与多个N沟道MIS晶体管的每一行形成的多个字线 沟道MIS晶体管，以及对应于多个N沟道MIS晶体管的每列形成的多个位线;以及P +扩散层，其形成为沿着多条字线延伸并提供有p阱电压电位的方向延伸 。

公开(公告)号：US20140287578A1

公开(公告)日：2014-09-25

申请号：US14297302

申请日：2014-06-05

申请人： Samsung Electronics Co., Ltd.

发明人： Jongwon Hong ,  Insun Park ,  Hei Seung Kim ,  Jongmin Baek

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  C25D3/38 ,  C25D5/08 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/522 ,  H01L27/04 ,  H01L27/1052 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein.

摘要翻译： 提供制造半导体器件的方法和由此制造的半导体器件。 在这些方法中，可以在单元凹槽区域和外围电路区域之间形成虚拟凹部区域。 由于存在虚拟凹部区域，因此可以降低在虚拟图案区域附近的镀液中所含的抑制剂的浓度梯度，使得抑制器的浓度在电池图案区域中更均匀，并且 向电池图案区域更有效地提供电流。 结果，可以在电池图案区域中更均匀地形成镀层，而不形成空穴。