公开(公告)号：US09973355B1

公开(公告)日：2018-05-15

申请号：US15133609

申请日：2016-04-20

Applicant: INPHI CORPORATION

Inventor： Dragos Cartina

IPC: H03H7/30 ,  H04L25/03 ,  G11C19/28 ,  H03K3/356

CPC classification number: H04L25/03057 ,  G11C19/28 ,  H03K3/356113

Abstract: The present invention is directed to communication systems and methods thereof. More specifically, an embodiment of the present invention includes a buffer that is coupled to a reference terminal. A shift register stores decision levels for post-cursor positions. A plurality of switches converts the decision levels to equalization currents during an equalization process. The equalization currents are converted to equalization voltage terms by one or more load resistors. The buffer is provided between the reference terminal and the one or more load resistors. There are other embodiments as well.

公开(公告)号：US11005690B1

公开(公告)日：2021-05-11

申请号：US16825637

申请日：2020-03-20

Applicant: INPHI CORPORATION

Inventor： Dragos Cartina ,  Ankit Bhargav ,  Jamal Riani ,  Wen-Sin Liew ,  Yu Liao ,  ChangFeng Loi

IPC: H04L25/03 ,  H04L25/02 ,  H04L25/49 ,  G01R19/25 ,  G01R13/34 ,  H03F1/32

Abstract: A device and method of operation for digital compensation of dynamic distortion. The transmitter device includes at least a digital-to-analog converter (DAC) connected to a lookup table (LUT), a first shift register, and a second shift register. The method includes iteratively adjusting the input values via the LUT to induce changes in the DAC output that compensate for dynamic distortion, which depends on precursors, current cursors, and postcursors. More specifically, the method includes producing and capturing average output values for each possible sequence of three symbols using the shift register and LUT configuration. Then, the LUT is updated with estimated values to induce desired output values that are adjusted to eliminate clipping. These steps are performed iteratively until one or more check conditions are satisfied. This method can also be combined with techniques such as equalization, eye modulation, and amplitude scaling to introduce desirable output signal characteristics.

公开(公告)号：US10263812B2

公开(公告)日：2019-04-16

申请号：US15951069

申请日：2018-04-11

Applicant: INPHI CORPORATION

Inventor： Dragos Cartina

IPC: H04L25/03 ,  G11C19/28 ,  H03K3/356

Abstract: The present invention is directed to communication systems and methods thereof. More specifically, an embodiment of the present invention includes a buffer that is coupled to a reference terminal. A shift register stores decision levels for post-cursor positions. A plurality of switches converts the decision levels to equalization currents during an equalization process. The equalization currents are converted to equalization voltage terms by one or more load resistors. The buffer is provided between the reference terminal and the one or more load resistors. There are other embodiments as well.