公开(公告)号：US11038538B2

公开(公告)日：2021-06-15

申请号：US16827355

申请日：2020-03-23

Applicant: INPHI CORPORATION

Inventor： Jamal Riani ,  Farshid Rafiee Rad ,  Benjamin P. Smith ,  Yu Liao ,  Sudeep Bhoja

IPC: H04L1/00 ,  H03M13/39

Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.

公开(公告)号：US10804913B1

公开(公告)日：2020-10-13

申请号：US16127103

申请日：2018-09-10

Applicant: INPHI CORPORATION

Inventor： Mrunmay Talegaonkar ,  Jorge Pernillo ,  Junyi Sun ,  Praveen Prabha ,  Chang-Feng Loi ,  Yu Liao ,  Jamal Riani ,  Belal Helal ,  Karthik Gopalakrishnan ,  Aaron Buchwald

IPC: H04L7/00 ,  H03L7/197 ,  H04L7/033 ,  H03L7/099 ,  H03L7/087 ,  H03L7/08

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

公开(公告)号：US10404289B1

公开(公告)日：2019-09-03

申请号：US15995036

申请日：2018-05-31

Applicant: INPHI CORPORATION

Inventor： Jamal Riani ,  Farshid Rafiee Rad ,  Benjamin Smith ,  Yu Liao ,  Sudeep Bhoja

IPC: H04L1/00 ,  H03M13/39

Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.

公开(公告)号：US11005690B1

公开(公告)日：2021-05-11

申请号：US16825637

申请日：2020-03-20

Applicant: INPHI CORPORATION

Inventor： Dragos Cartina ,  Ankit Bhargav ,  Jamal Riani ,  Wen-Sin Liew ,  Yu Liao ,  ChangFeng Loi

IPC: H04L25/03 ,  H04L25/02 ,  H04L25/49 ,  G01R19/25 ,  G01R13/34 ,  H03F1/32

Abstract: A device and method of operation for digital compensation of dynamic distortion. The transmitter device includes at least a digital-to-analog converter (DAC) connected to a lookup table (LUT), a first shift register, and a second shift register. The method includes iteratively adjusting the input values via the LUT to induce changes in the DAC output that compensate for dynamic distortion, which depends on precursors, current cursors, and postcursors. More specifically, the method includes producing and capturing average output values for each possible sequence of three symbols using the shift register and LUT configuration. Then, the LUT is updated with estimated values to induce desired output values that are adjusted to eliminate clipping. These steps are performed iteratively until one or more check conditions are satisfied. This method can also be combined with techniques such as equalization, eye modulation, and amplitude scaling to introduce desirable output signal characteristics.