公开(公告)号：US20170134034A1

公开(公告)日：2017-05-11

申请号：US15375029

申请日：2016-12-09

Applicant: INPHI CORPORATION

Inventor： Mohammad RANJBAR ,  Jorge PERNILLO

IPC: H03M1/10 ,  H03M1/38 ,  H03M1/68

CPC classification number: H03M1/1028 ,  H03K5/082 ,  H03M1/1023 ,  H03M1/36 ,  H03M1/38 ,  H03M1/662 ,  H03M1/68

Abstract: The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.