公开(公告)号：US12063049B2

公开(公告)日：2024-08-13

申请号：US17683916

申请日：2022-03-01

申请人： Anokiwave, Inc.

发明人： Eythan Familier ,  Kartik Sridharan ,  Jun Li ,  Gaurav Menon ,  Shamsun Nahar ,  Akhil Garlapati ,  Scott Humphreys ,  Antonio Geremia

IPC分类号： H03M1/10 ,  G04F10/00 ,  H03L7/197

CPC分类号： H03M1/1028 ,  G04F10/005 ,  H03L7/1976

摘要： Digital post-processing of time-to-digital converter (TDC) output data can be used to map each TDC code to the ideal one, but this requires knowing the TDC input-output mapping. Therefore, a calibration system and method are provided for characterizing operation of a TDC to compensate for non-idealities. Input signals having a known time difference are provided to the TDC, and a mapping between the TDC output and the known time difference is stored in a mapping table. With the described method, it is possible to input an input ramp of very low slope to construct this mapping to a desired resolution during a background calibration procedure. This characterizing and mapping can be performed across a range of input signals having different known time differences. After calibration, a mapping table can be used by a mapping circuit of the TDC or by a digital post-processing function to provide a compensated TDC output.

公开(公告)号：US11705915B2

公开(公告)日：2023-07-18

申请号：US17573555

申请日：2022-01-11

申请人： Samsung Electronics Co., Ltd.

发明人： Sangwook Park ,  Changkyoun Oh

IPC分类号： H03M1/06 ,  H03M1/10 ,  H04N17/00

CPC分类号： H03M1/1028 ,  H04N17/002

摘要： In a method of operating an analog-to-digital converter, a gain error and an offset error that are associated with a digital code generated from the analog-to-digital converter are obtained by performing a first analog-to-digital conversion on a first input analog signal. The gain error and the offset error are stored. A calibration digital code is generated by performing a second analog-to-digital conversion on a second input analog signal based on the gain error and the offset error.

公开(公告)号：US20230223947A1

公开(公告)日：2023-07-13

申请号：US17574299

申请日：2022-01-12

申请人： NXP USA, Inc.

发明人： Ronak Prakashchandra Trivedi ,  Hanqing Xing ,  See-Hoi Wong ,  Jean CauXuan Le ,  Ranga Seshu Paladugu

IPC分类号： H03M1/10

CPC分类号： H03M1/1028

摘要： A method for self-calibration of reference voltage drop in a Digital to Analog Converter (DAC) includes measuring each one of a plurality of thermometric weightages associated with a respective one of a plurality of thermometric bits, wherein the DAC includes a plurality of sub-binary bits and the plurality of thermometric bits. For each sequentially increasing combination of thermometric bit settings including at least two thermometric bits coupled to a high reference voltage and each sub-binary bit coupled to a low reference voltage, performing the steps of: determining a respective combined weightage correction; adding the combined weightage correction to the highest order bit of the combination of thermometric bit settings; and incrementing a number of bits of the combination of thermometric bit settings in response to the number of bits of the sequential combination being less than a total number of the plurality of thermometric bits.

公开(公告)号：US20230170915A1

公开(公告)日：2023-06-01

申请号：US17921698

申请日：2020-04-28

申请人： Telefonaktiebolaget LM Ericsson (publ)

发明人： Henrik Pia SJÖLAND ,  Mohammed ABDULAZIZ ,  Tony PÅHLSSON

IPC分类号： H03M1/10 ,  G04F10/00

CPC分类号： H03M1/1028 ,  G04F10/005

摘要： A calibration unit and method therein for calibrating a TDC comprised in a digital PLL are disclosed. The TDC receives a signal from a free-running DCO and a reference signal, and measures the time difference between the DCO and reference signals. The calibration unit receives and processes data samples output from the TDC and generates a calibration lookup table in which each TDC output value has a calibration value. The calibration lookup table may be used for post-distortion. For each TDC output level the corresponding calibration value from the lookup table may be added to the output of the TDC for correction.

公开(公告)号：US20170134034A1

公开(公告)日：2017-05-11

申请号：US15375029

申请日：2016-12-09

申请人： INPHI CORPORATION

发明人： Mohammad RANJBAR ,  Jorge PERNILLO

IPC分类号： H03M1/10 ,  H03M1/38 ,  H03M1/68

CPC分类号： H03M1/1028 ,  H03K5/082 ,  H03M1/1023 ,  H03M1/36 ,  H03M1/38 ,  H03M1/662 ,  H03M1/68

摘要： The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.

公开(公告)号：US09401726B2

公开(公告)日：2016-07-26

申请号：US14554790

申请日：2014-11-26

申请人： Silicon Laboratories Inc.

发明人： Kareem A. Ragab ,  John Khoury

IPC分类号： H03M1/10 ,  H03M1/06 ,  H03M1/12 ,  H03M1/00

CPC分类号： H03M1/1023 ,  H03M1/00 ,  H03M1/0626 ,  H03M1/0695 ,  H03M1/1004 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/124 ,  H03M2201/4233

摘要： A robust and fast background calibration technique for correction of time-interleaved ADC offset, gain, bandwidth, and timing mismatches is proposed. The technique combines the use of a calibration signal and a reference ADC. The calibration signal enhances robustness and makes the technique independent of the input signal's statistics. The reference ADC speeds up convergence and enables the use of a small amplitude calibration signal that does not significantly reduce the input signal dynamic range. The calibration signal can be subtracted or filtered from the ADC output and is therefore invisible to the ADC user.

摘要翻译： 提出了用于校正时间交织的ADC偏移，增益，带宽和时序不匹配的鲁棒且快速的背景校准技术。 该技术结合使用校准信号和参考ADC。 校准信号增强了鲁棒性，使得该技术独立于输入信号的统计。 参考ADC可以加快收敛速度​​，并且可以使用不会显着降低输入信号动态范围的小幅度校准信号。 校准信号可以从ADC输出中减去或滤波，因此ADC用户不可见。

公开(公告)号：US20160182075A1

公开(公告)日：2016-06-23

申请号：US14955905

申请日：2015-12-01

申请人： ANALOG DEVICES, INC.

发明人： SIDDHARTH DEVARAJAN ,  ERIC OTTE ,  NEVENA RAKULJIC ,  CARROLL C. SPEIR

IPC分类号： H03M1/10 ,  H03M1/46 ,  H03M1/12

CPC分类号： H03M1/128 ,  H03M1/1019 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/46 ,  H03M1/462 ,  H03M1/468 ,  H03M3/382 ,  H03M3/498

摘要： Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

摘要翻译： 模数转换器（ADC）可能会产生可能影响其性能的错误。 为了提高性能，已经使用许多技术来补偿或纠正错误。 当ADC采用亚微米技术实现时，ADC可以轻松轻松配备一个片上微处理器，用于执行各种数字功能。 片上微处理器和任何合适的数字电路可以实现减少这些错误的功能，从而能够减少某些不必要的伪像，并为高度可配置的ADC提供灵活的平台。 片上微处理器对于随机时间交织ADC特别有用。 此外，随机采样ADC可以并行添加到主ADC用于校准目的。 此外，整个系统可以包括用于校正ADC中的错误的有效实现。

公开(公告)号：US09300314B2

公开(公告)日：2016-03-29

申请号：US14054921

申请日：2013-10-16

申请人： ABB TECHNOLOGY AG

发明人： Joris Pascal ,  Richard Bloch

IPC分类号： H03M1/12 ,  H03M1/10

CPC分类号： H03M1/12 ,  H03M1/1004 ,  H03M1/1019 ,  H03M1/1028 ,  H03M1/129

摘要： An arrangement for reading out an analog voltage signal includes a voltage signal input for applying the analog voltage signal thereto, a reference unit configured to generate an analog reference voltage, and a converting unit configured to convert an analog input signal into a digital output signal. To enable online self-calibration of the arrangement, the arrangement includes a superposition unit configured to receive the analog voltage signal and the analog reference voltage. The superposition unit includes a modulation unit configured to generate a modulated reference voltage from the analog reference voltage. The superposition unit is configured to generate a combined analog signal by superimposing the modulated reference voltage onto the analog voltage signal, and to forward the combined analog signal to the converting unit.

摘要翻译： 用于读出模拟电压信号的装置包括用于向其施加模拟电压信号的电压信号，被配置为产生模拟参考电压的参考单元和被配置为将模拟输入信号转换为数字输出信号的转换单元。 为了实现布置的在线自校准，该布置包括被配置为接收模拟电压信号和模拟参考电压的叠加单元。 叠加单元包括被配置为从模拟参考电压产生调制参考电压的调制单元。 叠加单元被配置为通过将调制的参考电压叠加到模拟电压信号上来生成组合的模拟信号，并将组合的模拟信号转发到转换单元。

公开(公告)号：US09270291B1

公开(公告)日：2016-02-23

申请号：US14662001

申请日：2015-03-18

申请人： Broadcom Corporation

发明人： Gavin D. Parnaby ,  Vasudevan Parthasarathy ,  John S. Wang

IPC分类号： H03M1/12 ,  H03M1/10 ,  H04B17/21 ,  H04L7/00

CPC分类号： H03M1/121 ,  H03M1/0836 ,  H03M1/1028 ,  H03M1/1215 ,  H03M1/1245 ,  H04B17/21 ,  H04L7/0004

摘要： Methods and apparatuses are described for timing skew mitigation in time-interleaved ADCs (TI-ADCs) that may be performed for any receive signal without any special signals during blind initialization, which may be followed by background calibration. The same gain/skew calibration metrics may be applied to baud sampled and oversampled systems, including wideband receivers and regardless of any modulation, by applying a timing or frequency offset to non-stationary sampled signals during initial training. Skew mitigation is low latency, low power, low area, noise tolerant and scalable. Digital estimation may be implemented with accumulators and multipliers while analog calibration may be implemented with adjustable delays. DC and gain offsets may be calibrated before skew calibration. The slope of the correlation function between adjacent samples may be used to move a timing skew estimate stochastically at a low adaptive rate until the skew algorithm converges.

摘要翻译： 描述了用于在盲初始化期间可以对任何接收信号执行任何特殊信号的时间交织ADC（TI-ADC）中的定时偏移缓解的方法和装置，其可以在背景校准之后进行。 相同的增益/偏斜校准度量可以应用于波特率采样和过采样系统，包括宽带接收机，无论任何调制，通过在初始训练期间对非平稳采样信号应用定时或频率偏移。 倾斜减轻是低延迟，低功率，低面积，噪声容限和可扩展性。 数字估计可以用累加器和乘法器来实现，而模拟校准可以用可调延迟来实现。 在校准偏差之前可以校准直流和增益偏移。 相邻样本之间的相关函数的斜率可以用于以低自适应速率随机移动定时偏差估计，直到偏斜算法收敛。

公开(公告)号：USRE45343E1

公开(公告)日：2015-01-20

申请号：US13683139

申请日：2012-11-21

申请人： Intersil Americas Inc.

发明人： Sundar S. Kidambi

IPC分类号： H03M1/06

CPC分类号： H03M1/06 ,  H03M1/0624 ,  H03M1/1028 ,  H03M1/1215 ,  H04B1/16

摘要： Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). In order to obtain an error measure for offset, gain or phase, errors, outputs from each ADC are either summed or averaged over No samples. Calling each of the sums or averages as Xk where k=1, 2, . . . , M, there are M such values as a result. A single value representing the mean of these M values, Xmean, is chosen as a reference value. The offset, gain and phase errors for the M different ADCs are then obtained from Xk−Xmean. The sign of each offset error, i.e., sign (Xk−Xmean), is then used to drive an adaptive algorithm whose output represents an offset correction value for the corresponding ADC. The offset, gain, and phase correction outputs from the adaptive algorithm is fed to an array of Digital-to-Analog converters (DACs) whose outputs are voltages or currents that directly or indirectly controls the offset, gain or phase setting of each individual ADC. Thus, there are M different offset, gain and phase error signals and M different adaptive algorithms operating in conjunction with M different DACs providing offset control signals to M different ADCs. In certain embodiments, spur frequencies can be reduced with the use of notch filters.

摘要翻译： 用于校正M通道时间交织模数转换器（ADC）中元件失配的技术。 为了获得偏移，增益或相位误差的误差，错误，每个ADC的输出在无样本之间求和或平均。 将每个或者平均值调用为X k，其中k = 1,2。 。 。 ，M，结果有这样的M值。 选择表示这些M值的平均值的单个值Xmean作为参考值。 然后从Xk-Xmean获得M个不同ADC的偏移，增益和相位误差。 然后使用每个偏移误差的符号，即符号（Xk-Xmean）来驱动自适应算法，其自适应算法的输出表示对应的ADC的偏移校正值。 来自自适应算法的偏移，增益和相位校正输出被馈送到数模转换器（DAC）阵列，数字模拟转换器（DAC）的输出是直接或间接控制每个ADC的偏移，增益或相位设置的电压或电流 。 因此，存在M个不同的偏移，增益和相位误差信号，以及M个不同的自适应算法，与M个不同的DAC结合，为M个不同的ADC提供偏移控制信号。 在某些实施例中，使用陷波滤波器可以减少杂散频率。