公开(公告)号：US11651092B2

公开(公告)日：2023-05-16

申请号：US17237102

申请日：2021-04-22

Applicant: INTEL CORPORATION

Inventor： Brian S. Hausauer ,  Lokpraveen B. Mosur ,  Tony Hurson ,  Patrick Fleming ,  Adrian R. Pearson

IPC: G06F21/62 ,  H04L9/40 ,  G06F21/78 ,  H04L9/32 ,  H04L9/08 ,  H04L67/1097 ,  G06F16/13

CPC classification number: G06F21/62 ,  G06F21/78 ,  H04L9/0891 ,  H04L9/0894 ,  H04L9/3242 ,  H04L63/0428 ,  H04L63/06 ,  H04L63/08 ,  H04L63/10 ,  G06F16/13 ,  G06F2221/2107 ,  H04L9/3213 ,  H04L67/1097

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine a secure memory region for a transaction, the secure memory region associated with a security association context to perform one or more of an encryption/decryption operation and an authentication operation for the transaction, perform one or more of the encryption/decryption operation and the authentication operation for the transaction based on the security association context, and cause communication of the transaction.

公开(公告)号：US11042657B2

公开(公告)日：2021-06-22

申请号：US15721769

申请日：2017-09-30

Applicant: INTEL CORPORATION

Inventor： Brian S. Hausauer ,  Lokpraveen B. Mosur ,  Tony Hurson ,  Patrick Fleming ,  Adrian R. Pearson

IPC: G06F21/62 ,  H04L29/06 ,  G06F21/78 ,  H04L9/32 ,  H04L9/08 ,  H04L29/08 ,  G06F16/13

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to de determine a secure memory region for a transaction, the secure memory region associated with a security association context to perform one or more of an encryption/decryption operation and an authentication operation for the transaction, perform one or more of the encryption/decryption operation and the authentication operation for the transaction based on the security association context, and cause communication of the transaction.

公开(公告)号：US12212502B2

公开(公告)日：2025-01-28

申请号：US17084526

申请日：2020-10-29

Applicant: Intel Corporation

Inventor： Mark Debbage ,  Robert Southworth ,  Arvind Srinivasan ,  Cheolmin Park ,  Todd Rimmer ,  Brian S. Hausauer

IPC: H04L47/34 ,  H04L1/1607 ,  H04L47/125

Abstract: Examples described herein relate to technologies for reliable packet transmission. In some examples, a network interface includes circuitry to: receive a request to transmit a packet to a destination device, select a path for the packet, provide a path identifier identifying one of multiple paths from the network interface to a destination and Path Sequence Number (PSN) for the packet, wherein the PSN is to identify a packet transmission order over the selected path, include the PSN in the packet, and transmit the packet. In some examples, if the packet is a re-transmit of a previously transmitted packet, the circuitry is to: select a path for the re-transmit packet, and set a PSN of the re-transmit packet that is a current packet transmission number for the selected path for the re-transmit packet. In some examples, a network interface includes circuitry to process a received packet to at least determine a Path Sequence Number (PSN) for the received packet, wherein the PSN is to provide an order of packet transmissions for a path associated with the received packet, process a second received packet to at least determine its PSN, and based on the PSN of the second received packet not being a next sequential value after the PSN of the received packet, cause transmission of a re-transmit request to a sender of the packet and the second packet.

公开(公告)号：US09507752B2

公开(公告)日：2016-11-29

申请号：US13628771

申请日：2012-09-27

Applicant: Intel Corporation

Inventor： Vadim Makhervaks ,  Kenneth G. Keels ,  Brian S. Hausauer ,  Ali S. Oztaskin

IPC: G06F15/167 ,  G06F15/173

CPC classification number: G06F15/17331

Abstract: Methods, apparatus and systems for reducing usage of Doorbell Rings in connection with RDMA operations. A portion of system memory is employed as a Memory-Mapped Input/Output (MMIO) address space configured to be accessed via a hardware networking device. A Send Queue (SQ) is stored in MMIO and is used to facilitate processing of Work Requests (WRs) that are written to SQ entries by software and read from the SQ via the hardware networking device. The software and logic in the hardware networking device employ pointers identifying locations in the SQ corresponding to a next write WR entry slot and last read WR entry slot that are implemented to enable WRs to be written to and read from the SQ during ongoing operations under which the SQ is not emptied such that doorbell rings to notify the hardware networking device that new WRs have been written to the SQ are not required.

Abstract translation: 与RDMA操作相关的减少门铃环使用的方法，装置和系统。 系统存储器的一部分被用作经配置以经由硬件网络设备访问的存储器映射输入/输出（MMIO）地址空间。 发送队列（SQ）存储在MMIO中，用于促进通过软件写入SQ条目并通过硬件网络设备从SQ读取的工作请求（WR）的处理。 硬件网络设备中的软件和逻辑采用标识SQ中相应于下一个写入WR入口时隙的位置的指针，以及最后读取的WR入口时隙，其被实现为使得在正在进行的操作期间将WR写入到SQ并从其读取， SQ不能清空，以致门铃振铃以通知硬件网络设备不会向SQ写入新的WR。