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    Reliable transport architecture
    1.
    发明授权
    Reliable transport architecture 有权

    公开(公告)号：US12212502B2

    公开(公告)日：2025-01-28

    申请号：US17084526

    申请日：2020-10-29

    Applicant: Intel Corporation

    Inventor： Mark Debbage ,  Robert Southworth ,  Arvind Srinivasan ,  Cheolmin Park ,  Todd Rimmer ,  Brian S. Hausauer

    IPC: H04L47/34 ,  H04L1/1607 ,  H04L47/125

    Abstract: Examples described herein relate to technologies for reliable packet transmission. In some examples, a network interface includes circuitry to: receive a request to transmit a packet to a destination device, select a path for the packet, provide a path identifier identifying one of multiple paths from the network interface to a destination and Path Sequence Number (PSN) for the packet, wherein the PSN is to identify a packet transmission order over the selected path, include the PSN in the packet, and transmit the packet. In some examples, if the packet is a re-transmit of a previously transmitted packet, the circuitry is to: select a path for the re-transmit packet, and set a PSN of the re-transmit packet that is a current packet transmission number for the selected path for the re-transmit packet. In some examples, a network interface includes circuitry to process a received packet to at least determine a Path Sequence Number (PSN) for the received packet, wherein the PSN is to provide an order of packet transmissions for a path associated with the received packet, process a second received packet to at least determine its PSN, and based on the PSN of the second received packet not being a next sequential value after the PSN of the received packet, cause transmission of a re-transmit request to a sender of the packet and the second packet.

    METHOD, APPARATUS, AND SYSTEM FOR QOS WITHIN HIGH PERFORMANCE FABRICS
    3.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR QOS WITHIN HIGH PERFORMANCE FABRICS 审中-公开

    公开(公告)号：US20170237671A1

    公开(公告)日：2017-08-17

    申请号：US15585366

    申请日：2017-05-03

    Applicant: Intel Corporation

    Inventor： Todd Rimmer ,  Thomas D. Lovett ,  Albert Cheng

    IPC: H04L12/851 ,  H04L12/931 ,  H04L29/06

    CPC classification number: H04L47/2425 ,  H04L47/2408 ,  H04L47/2458 ,  H04L47/2491 ,  H04L49/10 ,  H04L49/3045 ,  H04L49/358 ,  H04L49/70 ,  H04L69/22

    Abstract: Method, apparatus, and systems for implementing Quality of Service (QoS) within high performance fabrics. A multi-level QoS scheme is implemented including virtual fabrics, Traffic Classes, Service Levels (SLs), Service Channels (SCs) and Virtual Lanes (VLs). SLs are implemented for Layer 4 (Transport Layer) end-to-end transfer of fabric packets, while SCs are used to differentiate fabric packets at the Link Layer. Fabric packets are divided into flits, with fabric packet data transmitted via fabric links as flits streams. Fabric switch input ports and device receive ports detect SC IDs for received fabric packets and implement SC-to-VL mappings to determine VL buffers to buffer fabric packet flits in. An SL may have multiple SCs, and SC-to-SC mapping may be implemented to change the SC for a fabric packet as it is forwarded through the fabric, while maintaining its SL. A Traffic Class may include multiple SLs, enabling request and response traffic for an application to employ separate SLs.

    Buffer allocation for parallel processing of data by message passing interface (MPI)
    4.
    发明授权
    Buffer allocation for parallel processing of data by message passing interface (MPI) 有权

    公开(公告)号：US12170625B2

    公开(公告)日：2024-12-17

    申请号：US16944072

    申请日：2020-07-30

    Applicant: Intel Corporation

    Inventor： Todd Rimmer ,  Sayantan Sur ,  Michael William Heinz

    IPC: H04L12/54 ,  G06F15/173 ,  H04L49/90 ,  H04L49/9047

    Abstract: Examples described herein relate to receiving, at a network interface, an allocation of a first group of one or more buffers to store data to be processed by a Message Passing Interface (MPI) and based on a received packet including an indicator that permits the network interface to select a buffer for the received packet and store the received packet in the selected buffer, the network interface storing a portion of the received packet in a buffer of the first group of the one or more buffers. The indicator can permit the network interface to select a buffer for the received packet and store the received packet in the selected buffer irrespective of a tag and sender associated with the received packet. In some examples, based on a received packet including an indicator that does not permit storage of the received packet in a buffer irrespective of a tag and source associated with the second received packet, the network interface is to store a portion of the second received packet in a buffer of the second group of one or more buffers, wherein the buffer of the second group of one or more buffers corresponds to a tag and source associated with the second received packet.

    TRANSPORT OF ETHERNET PACKET DATA WITH WIRE-SPEED AND PACKET DATA RATE MATCH
    7.
    发明申请
    TRANSPORT OF ETHERNET PACKET DATA WITH WIRE-SPEED AND PACKET DATA RATE MATCH 有权
    以太网分组数据的传输与线速和分组数据速率匹配

    公开(公告)号：US20150222533A1

    公开(公告)日：2015-08-06

    申请号：US14173782

    申请日：2014-02-05

    Applicant: INTEL CORPORATION

    Inventor： Mark S. Birrittella ,  Thomas D. Lovett ,  Todd Rimmer

    IPC: H04L12/721 ,  H04L12/947 ,  H04L12/741

    CPC classification number: H04L45/745 ,  H04L5/0055 ,  H04L45/66 ,  H04L45/74 ,  H04L47/17 ,  H04L47/39 ,  H04L49/25 ,  H04L61/3075 ,  H04Q2213/13215

    Abstract: Method, apparatus, and systems for reliably transferring Ethernet packet data over a link layer and facilitating fabric-to-Ethernet and Ethernet-to-fabric gateway operations at matching wire speed and packet data rate. Ethernet header and payload data is extracted from Ethernet frames received at the gateway and encapsulated in fabric packets to be forwarded to a fabric endpoint hosting an entity to which the Ethernet packet is addressed. The fabric packets are divided into flits, which are bundled in groups to form link packets that are transferred over the fabric at the Link layer using a reliable transmission scheme employing implicit ACKnowledgements. At the endpoint, the fabric packet is regenerated, and the Ethernet packet data is de-encapsulated. The Ethernet frames received from and transmitted to an Ethernet network are encoded using 64b/66b encoding, having an overhead-to-data bit ratio of 1:32. Meanwhile, the link packets have the same ratio, including one overhead bit per flit and a 14-bit CRC plus a 2-bit credit return field or sideband used for credit-based flow control.

    Abstract translation: 用于通过链路层可靠地传输以太网分组数据的方法，装置和系统，并且以匹配的线速度和分组数据速率促进以太网和以太网到网络的网关操作。 从网关接收的以太网帧提取以太网报头和有效载荷数据，并将其封装在结构数据包中，以转发到托管以太网数据包所针对的实体的结构端点。 结构分组被划分成flits，它们被分组成组，以形成通过使用隐式确认的可靠传输方案在链路层上通过结构传送的链路分组。 在端点，重新生成Fabric数据包，并对以太网数据包进行解封装。 从以太网网络接收并发送到以太网的以太网帧使用64b / 66b编码进行编码，具有1:32的开销数据比特率。 同时，链路分组具有相同的比率，包括一个开销比特每个flit和一个14比特CRC加上一个2比特的信用回报字段或用于基于信用的流量控制的边带。

    Hierarchical/lossless packet preemption to reduce latency jitter in flow-controlled packet-based networks
    8.
    发明授权
    Hierarchical/lossless packet preemption to reduce latency jitter in flow-controlled packet-based networks 有权

    公开(公告)号：US10230665B2

    公开(公告)日：2019-03-12

    申请号：US14136293

    申请日：2013-12-20

    Applicant: INTEL CORPORATION

    Inventor： Thomas D. Lovett ,  Albert Cheng ,  Mark S. Birrittella ,  James Kunz ,  Todd Rimmer

    IPC: H04L12/933 ,  H04L12/911 ,  H04L1/00 ,  H04L12/851 ,  H04L12/805 ,  H04L12/863 ,  H04L12/865 ,  H04L1/12 ,  H04L25/14

    Abstract: Methods, apparatus, and systems for implementing hierarchical and lossless packet preemption and interleaving to reduce latency jitter in flow-controller packet-based networks. Fabric packets are divided into a plurality of data units, with data units for different fabric packets buffered in separate buffers. Data units are pulled from the buffers and added to a transmit stream in which groups of data units are interleaved. Upon receipt by a receiver, the groups of data units are separated out and buffered in separate buffers under which data units for the same fabric packets are grouped together. In one aspect, each buffer is associated with a respective virtual lane (VL), and the fabric packets are effectively transferred over fabric links using virtual lanes. VLs may have different levels of priority under which data units for fabric packets in higher-priority VLs may preempt fabric packets in lower-priority VLs. By transferring data units rather than entire packets, transmission of a packet can be temporarily paused in favor of a higher-priority packet. Multiple levels of preemption and interleaving in a nested manner are supported.

    System, method and apparatus for improving the performance of collective operations in high performance computing
    9.
    发明授权
    System, method and apparatus for improving the performance of collective operations in high performance computing 有权

    公开(公告)号：US10015056B2

    公开(公告)日：2018-07-03

    申请号：US15207706

    申请日：2016-07-12

    Applicant: Intel Corporation

    Inventor： Michael Heinz ,  Todd Rimmer ,  James Kunz ,  Mark Debbage

    IPC: H04L12/28 ,  H04L12/24 ,  H04L12/753 ,  H04L12/751 ,  G06F9/50

    CPC classification number: H04L41/12 ,  G06F9/5066 ,  H04L41/0213 ,  H04L41/046 ,  H04L41/0893 ,  H04L45/08 ,  H04L45/48

    Abstract: System, method, and apparatus for improving the performance of collective operations in High Performance Computing (HPC). Compute nodes in a networked HPC environment form collective groups to perform collective operations. A spanning tree is formed including the compute nodes and switches and links used to interconnect the compute nodes, wherein the spanning tree is configured such that there is only a single route between any pair of nodes in the tree. The compute nodes implement processes for performing the collective operations, which includes exchanging messages between processes executing on other compute nodes, wherein the messages contain indicia identifying collective operations they belong to. Each switch is configured to implement message forwarding operations for its portion of the spanning tree. Each of the nodes in the spanning tree implements a ratcheted cyclical state machine that is used for synchronizing collective operations, along with status messages that are exchanged between nodes. Transaction IDs are also used to detect out-of-order and lost messages.

    Reliable transport of ethernet packet data with wire-speed and packet data rate match
    10.
    发明授权
    Reliable transport of ethernet packet data with wire-speed and packet data rate match 有权

    公开(公告)号：US09628382B2

    公开(公告)日：2017-04-18

    申请号：US14173782

    申请日：2014-02-05

    Applicant: INTEL CORPORATION

    Inventor： Mark S. Birrittella ,  Thomas D. Lovett ,  Todd Rimmer

    IPC: H04L12/721 ,  H04L12/741 ,  H04L12/947

    CPC classification number: H04L45/745 ,  H04L5/0055 ,  H04L45/66 ,  H04L45/74 ,  H04L47/17 ,  H04L47/39 ,  H04L49/25 ,  H04L61/3075 ,  H04Q2213/13215

    Abstract: Method, apparatus, and systems for reliably transferring Ethernet packet data over a link layer and facilitating fabric-to-Ethernet and Ethernet-to-fabric gateway operations at matching wire speed and packet data rate. Ethernet header and payload data is extracted from Ethernet frames received at the gateway and encapsulated in fabric packets to be forwarded to a fabric endpoint hosting an entity to which the Ethernet packet is addressed. The fabric packets are divided into flits, which are bundled in groups to form link packets that are transferred over the fabric at the Link layer using a reliable transmission scheme employing implicit ACKnowledgements. At the endpoint, the fabric packet is regenerated, and the Ethernet packet data is de-encapsulated. The Ethernet frames received from and transmitted to an Ethernet network are encoded using 64b/66b encoding, having an overhead-to-data bit ratio of 1:32. Meanwhile, the link packets have the same ratio, including one overhead bit per flit and a 14-bit CRC plus a 2-bit credit return field or sideband used for credit-based flow control.

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