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    Managing congestion in a network
    2.
    发明授权
    Managing congestion in a network 有权

    公开(公告)号：US10944660B2

    公开(公告)日：2021-03-09

    申请号：US16517408

    申请日：2019-07-19

    Applicant: Intel Corporation

    Inventor： Tony Hurson ,  Simoni Ben-Michael ,  Ben-Zion Friedman

    IPC: H04L12/26 ,  H04L29/08 ,  H04L12/801 ,  H04L12/863

    Abstract: Examples described herein include configuration of a transmitting network device to identify a source queue-pair identifier in at least some of the packets that are transmitted to an endpoint destination. A network device that receives packets and experiences congestion can determine if a congestion causing packet includes a source queue-pair identifier. If the congestion causing packet includes a source queue-pair identifier, the network device can form and transmit a congestion notification message with a copy of the source queue-pair identifier to the transmitting network device. The transmitting network device can access a context for the congestion causing packet using the source queue-pair identifier without having to perform a lookup to identify the context.

    Data consistency and durability over distributed persistent memory systems
    8.
    发明授权
    Data consistency and durability over distributed persistent memory systems 有权

    公开(公告)号：US11709774B2

    公开(公告)日：2023-07-25

    申请号：US16986094

    申请日：2020-08-05

    Applicant: Intel Corporation

    Inventor： Ren Wang ,  Yifan Yuan ,  Yipeng Wang ,  Tsung-Yuan C. Tai ,  Tony Hurson

    IPC: G06F13/16 ,  G06F12/0804 ,  G06F16/23 ,  G06F12/08

    CPC classification number: G06F12/0804 ,  G06F13/1668 ,  G06F16/2365

    Abstract: Examples described herein relates to a network interface apparatus that includes packet processing circuitry and a bus interface. In some examples, the packet processing circuitry to: process a received packet that includes data, a request to perform a write operation to write the data to a cache, and an indicator that the data is to be durable and based at least on the received packet including the request and the indicator, cause the data to be written to the cache and non-volatile memory. In some examples, the packet processing circuitry is to issue a command to an input output (IO) controller to cause the IO controller to write the data to the cache and the non-volatile memory. In some examples, the cache comprises one or more of: a level-0 (L0), level-1 (L1), level-2 (L2), or last level cache (LLC) and the non-volatile memory comprises one or more of: volatile memory that is part of an Asynchronous DRAM Refresh (ADR) domain, persistent memory, battery-backed memory, or memory device whose state is determinate even if power is interrupted to the memory device. In some examples, based on receipt of a second received packet that includes a request to persist data, the packet processing circuitry is to request that data stored in a memory buffer be copied to the non-volatile memory.

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