公开(公告)号：US20230042934A1

公开(公告)日：2023-02-09

申请号：US17560170

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Utkarsh Y. KAKAIYA ,  Philip LANTZ ,  Sanjay KUMAR ,  Rajesh SANKARAN ,  Narayan RANGANATHAN ,  Saurabh GAYEN ,  Dhananjay JOSHI ,  Nikhil P. RAO

IPC: G06F11/07

Abstract: Apparatus and method for high-performance page fault handling. For example, one embodiment of an apparatus comprises: one or more accelerator engines to process work descriptors submitted by clients to a plurality of work queues; fault processing hardware logic associated with the one or more accelerator engines, the fault processing hardware logic to implement a specified page fault handling mode for each work queue of the plurality of work queues, the page fault handling modes including a first page fault handling mode and a second page fault handling mode.

公开(公告)号：US20230040226A1

公开(公告)日：2023-02-09

申请号：US17559612

申请日：2021-12-22

Applicant: INTEL CORPORATION

Inventor： Saurabh GAYEN ,  Dhananjay JOSHI ,  Philip LANTZ ,  Rajesh SANKARAN ,  Narayan RANGANATHAN

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/30

Abstract: Apparatus and method for managing pipeline depth of a data processing device. For example, one embodiment of an apparatus comprises: an interface to receive a plurality of work requests from a plurality of clients; and a plurality of engines to perform the plurality of work requests; wherein the work requests are to be dispatched to the plurality of engines from a plurality of work queues, the work queues to store a work descriptor per work request, each work descriptor to include information needed to perform a corresponding work request, wherein the plurality of work queues include a first work queue to store work descriptors associated with first latency characteristics and a second work queue to store work descriptors associated with second latency characteristics; engine configuration circuitry to configure a first engine to have a first pipeline depth based on the first latency characteristics and to configure a second engine to have a second pipeline depth based on the second latency characteristics.