公开(公告)号：US20250117264A1

公开(公告)日：2025-04-10

申请号：US18935248

申请日：2024-11-01

Applicant: Intel Corporation

Inventor： Utkarsh Y. KAKAIYA ,  Rajesh M. SANKARAN ,  Sanjay KUMAR ,  Kun TIAN ,  Philip LANTZ

IPC: G06F9/54 ,  G06F9/455 ,  G06F9/48 ,  G06F15/17

Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

公开(公告)号：US20230171145A1

公开(公告)日：2023-06-01

申请号：US17446974

申请日：2021-09-06

Applicant: Intel Corporation

Inventor： Mona HOSSAIN ,  Sanjay KUMAR ,  Utkarsh Y. KAKAIYA

IPC: H04L12/24

CPC classification number: H04L41/06 ,  H04L41/14

Abstract: A server is provided. The server comprises one or more interfaces configured to communicate with a client and processing circuitry configured to control the one or more interfaces and to transmit an interrupt to the client informing the client about an operation state of the server.

公开(公告)号：US20220107910A1

公开(公告)日：2022-04-07

申请号：US17550977

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Sanjay KUMAR ,  Rajesh M. SANKARAN ,  Philip R. LANTZ ,  Utkarsh Y. KAKAIYA ,  Kun TIAN

IPC: G06F13/24 ,  G06F9/455 ,  G06F9/48

Abstract: Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.

公开(公告)号：US20230251912A1

公开(公告)日：2023-08-10

申请号：US18301733

申请日：2023-04-17

Applicant: Intel Corporation

Inventor： Utkarsh Y. KAKAIYA ,  Rajesh SANKARAN ,  Sanjay KUMAR ,  Kun TIAN ,  Philip LANTZ

IPC: G06F9/50 ,  G06F15/76 ,  H04L51/226

CPC classification number: G06F9/5077 ,  G06F9/5038 ,  G06F15/76 ,  H04L51/226 ,  H04T2001/2093 ,  G06F15/17

Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

公开(公告)号：US20210373934A1

公开(公告)日：2021-12-02

申请号：US17404897

申请日：2021-08-17

Applicant: Intel Corporation

Inventor： Sanjay KUMAR ,  Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Philip R. LANTZ ,  Jason W. BRANDT ,  Vedvyas SHANBHOGUE ,  Utkarsh Y. KAKAIYA ,  Kun TIAN

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1045 ,  G06F12/109

Abstract: Implementations of the disclosure provide a processing device comprising an address translation circuit to intercept a work request from an I/O device. The work request comprises a first ASID to map to a work queue. A second ASID of a host is allocated for the first ASID based on the work queue. The second ASID is allocated to at least one of: an ASID register for a dedicated work queue (DWQ) or an ASID translation table for a shared work queue (SWQ). Responsive to receiving a work submission from the SVM client to the I/O device, the first ASID of the application container is translated to the second ASID of the host machine for submission to the I/O device using at least one of: the ASID register for the DWQ or the ASID translation table for the SWQ based on the work queue associated with the I/O device.

公开(公告)号：US20240184739A1

公开(公告)日：2024-06-06

申请号：US18432859

申请日：2024-02-05

Applicant: INTEL CORPORATION

Inventor： Joydeep RAY ,  Niranjan COORAY ,  Subramaniam MAIYURAN ,  Altug KOKER ,  Prasoonkumar SURTI ,  Varghese GEORGE ,  Valentin ANDREI ,  Abhishek APPU ,  Guadalupe GARCIA ,  Pattabhiraman K ,  Sungye KIM ,  Sanjay KUMAR ,  Pratik MAROLIA ,  Elmoustapha OULD-AHMED-VALL ,  Vasanth RANGANATHAN ,  William SADLER ,  Lakshminarayanan STRIRAMASSARMA

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

公开(公告)号：US20230283512A2

公开(公告)日：2023-09-07

申请号：US17446974

申请日：2021-09-06

Applicant: Intel Corporation

Inventor： Mona HOSSAIN ,  Sanjay KUMAR ,  Utkarsh KAKAIYA

IPC: H04L12/24

CPC classification number: H04L41/06 ,  H04L41/14

Abstract: A server is provided. The server comprises one or more interfaces configured to communicate with a client and processing circuitry configured to control the one or more interfaces and to transmit an interrupt to the client informing the client about an operation state of the server.

公开(公告)号：US20230042934A1

公开(公告)日：2023-02-09

申请号：US17560170

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Utkarsh Y. KAKAIYA ,  Philip LANTZ ,  Sanjay KUMAR ,  Rajesh SANKARAN ,  Narayan RANGANATHAN ,  Saurabh GAYEN ,  Dhananjay JOSHI ,  Nikhil P. RAO

IPC: G06F11/07

Abstract: Apparatus and method for high-performance page fault handling. For example, one embodiment of an apparatus comprises: one or more accelerator engines to process work descriptors submitted by clients to a plurality of work queues; fault processing hardware logic associated with the one or more accelerator engines, the fault processing hardware logic to implement a specified page fault handling mode for each work queue of the plurality of work queues, the page fault handling modes including a first page fault handling mode and a second page fault handling mode.

公开(公告)号：US20220027207A1

公开(公告)日：2022-01-27

申请号：US17361932

申请日：2021-06-29

Applicant: Intel Corporation

Inventor： Utkarsh Y. KAKAIYA ,  Rajesh SANKARAN ,  Sanjay KUMAR ,  Kun TIAN ,  Philip LANTZ

IPC: G06F9/50 ,  H04L12/58 ,  G06F15/76

Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

公开(公告)号：US20210004334A1

公开(公告)日：2021-01-07

申请号：US16772765

申请日：2018-03-28

Applicant: INTEL CORPORATION

Inventor： Kun TIAN ,  Xiao ZHENG ,  Ashok RAJ ,  Sanjay KUMAR ,  Rajesh SANKARAN

IPC: G06F12/1036 ,  G06F9/455 ,  G06F12/1081

Abstract: Embodiment of this disclosure provides a mechanism to extend a workload instruction to include both untranslated and translated address space identifiers (ASIDs). In one embodiment, a processing device comprising a translation manager is provided. The translation manager receives a workload instruction from a guest application. The workload instruction comprises an untranslated (ASID) and a workload for an input/output (I/O) device. The untranslated ASID is translated to a translated ASID. The translated ASID inserted into a payload of the workload instruction. Thereupon, the payload is provided to a work queue of the I/O device to execute the workload based in part on at least one of: the translated ASID or the untranslated ASID.