公开(公告)号：US20140223145A1

公开(公告)日：2014-08-07

申请号：US13992797

申请日：2011-12-30

Applicant: INTEL CORPORATION

Inventor： Srihari Makineni ,  Steven R. King ,  Zhen Fang ,  Alexander Redkin ,  Ravishankar Iyer ,  Pavel S. Smirnov ,  Dmitry Gusev ,  Dmitri Pavlov ,  May Wu

IPC: G06F9/30

CPC classification number: G06F9/30076 ,  G06F1/32 ,  G06F9/30196 ,  G06F9/3822 ,  G06F9/3891

Abstract: A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant.

Abstract translation: 处理器可以用仅执行需要完全向后兼容的一些部分指令集的核来构建。 因此，在一些实施例中，可以通过提供仅执行特定指令而不是其他指令的部分核来降低功耗。 不支持的指令可以以其他更节能的方式处理，使得包括部分核心的整体处理器可以完全向后兼容。

公开(公告)号：US09753732B2

公开(公告)日：2017-09-05

申请号：US15175427

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： Xiaowei Jiang ,  Srihari Makineni ,  Zhen Fang ,  Dmitri Pavlov ,  Ravi Iyer

IPC: G06F9/00 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058

Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.

公开(公告)号：US20160283244A1

公开(公告)日：2016-09-29

申请号：US15175427

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： Xiaowei Jiang ,  Srihari Makineni ,  Zhen Fang ,  Dmitri Pavlov ,  Ravi Iyer

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058

Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.

Abstract translation: 根据本发明的一些实施例，用于嵌入式控制器的分支预测单元可以与指令提取单元相关联而不是解码级放置。 另外，分支预测单元也可以不包括分支预测器。 此外，返回地址堆栈可以与指令解码级相关联，并且在结构上与分支预测单元分离。 在某些情况下，这种布置减少了分支预测单元的面积以及功耗。