公开(公告)号：US20160283244A1

公开(公告)日：2016-09-29

申请号：US15175427

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： Xiaowei Jiang ,  Srihari Makineni ,  Zhen Fang ,  Dmitri Pavlov ,  Ravi Iyer

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058

Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.

Abstract translation: 根据本发明的一些实施例，用于嵌入式控制器的分支预测单元可以与指令提取单元相关联而不是解码级放置。 另外，分支预测单元也可以不包括分支预测器。 此外，返回地址堆栈可以与指令解码级相关联，并且在结构上与分支预测单元分离。 在某些情况下，这种布置减少了分支预测单元的面积以及功耗。

公开(公告)号：US09047171B2

公开(公告)日：2015-06-02

申请号：US13631894

申请日：2012-09-29

Applicant: Intel Corporation

Inventor： Zhen Fang ,  Shih-Lien Lu ,  Ravishankar Iyer ,  Srihari Makineni

IPC: G06F12/00 ,  G06F11/00 ,  G06F1/32 ,  G11C5/14

CPC classification number: G06F11/004 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3296 ,  G11C5/14 ,  G11C5/141 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

Abstract: Systems and methods may provide for determining whether a memory access request is error-tolerant, and routing the memory access request to a reliable memory region if the memory access request is error-tolerant. Moreover, the memory access request may be routed to an unreliable memory region if the memory access request is error-tolerant. In one example, use of the unreliable memory region enables a reduction in the minimum operating voltage level for a die containing the reliable and unreliable memory regions.

Abstract translation: 系统和方法可以提供确定存储器访问请求是否是容错的，以及如果存储器访问请求是容错的，则将存储器访问请求路由到可靠的存储器区域。 此外，如果存储器访问请求是容错的，则存储器访问请求可以被路由到不可靠的存储器区域。 在一个示例中，使用不可靠的存储区域使得能够降低包含可靠和不可靠的存储器区域的管芯的最小工作电压电平。

公开(公告)号：US10095520B2

公开(公告)日：2018-10-09

申请号：US15194558

申请日：2016-06-27

Applicant: Intel Corporation

Inventor： Zhen Fang ,  Xiaowei Jiang ,  Srihari Makineni ,  Rameshkumar G. Illikkal ,  Ravishankar Iyer

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F13/24 ,  G06F9/48

Abstract: An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.

公开(公告)号：US09753732B2

公开(公告)日：2017-09-05

申请号：US15175427

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： Xiaowei Jiang ,  Srihari Makineni ,  Zhen Fang ,  Dmitri Pavlov ,  Ravi Iyer

IPC: G06F9/00 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058

Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.

公开(公告)号：US20140223145A1

公开(公告)日：2014-08-07

申请号：US13992797

申请日：2011-12-30

Applicant: INTEL CORPORATION

Inventor： Srihari Makineni ,  Steven R. King ,  Zhen Fang ,  Alexander Redkin ,  Ravishankar Iyer ,  Pavel S. Smirnov ,  Dmitry Gusev ,  Dmitri Pavlov ,  May Wu

IPC: G06F9/30

CPC classification number: G06F9/30076 ,  G06F1/32 ,  G06F9/30196 ,  G06F9/3822 ,  G06F9/3891

Abstract: A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant.

Abstract translation: 处理器可以用仅执行需要完全向后兼容的一些部分指令集的核来构建。 因此，在一些实施例中，可以通过提供仅执行特定指令而不是其他指令的部分核来降低功耗。 不支持的指令可以以其他更节能的方式处理，使得包括部分核心的整体处理器可以完全向后兼容。

公开(公告)号：US08762599B2

公开(公告)日：2014-06-24

申请号：US13729172

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Michael J. Espig ,  Zhen Fang ,  Ravishankar Iyer ,  David J. Harriman

IPC: G06F3/00

CPC classification number: G06F13/24 ,  G06F9/542

Abstract: In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于处理从主机处理器接收的注册消息的方法，其中所述注册消息将关于设备的轮询操作从主机处理器委托给另一个组件。 来自消息的信息可以存储在轮询表中，并且组件可以发送读请求以轮询该设备并且基于该设备的状态向轮询处理器报告轮询的结果。 描述和要求保护其他实施例。