公开(公告)号：US20250062610A1

公开(公告)日：2025-02-20

申请号：US18399290

申请日：2023-12-28

Applicant: INTEL CORPORATION

Inventor： Harel Aronheim ,  Dmitry Felsenstein ,  Ariel Wolf ,  Eran Amir ,  Ofir Klein ,  Yazan Alwilly ,  Sergey Sofer ,  Sagi Belizowski

IPC: H02J1/14

Abstract: For example, a current consumption adjuster may be configured to adjust a current consumption from a power supply of an integrated circuit. For example, the current consumption adjuster may include a controllable load circuitry to controllably apply one or more loads to the power supply of the integrated circuit. For example, the current consumption adjuster may include a controller configured to identify a current consumption event including a transition of a current consumption of the integrated circuit from the power supply. For example, the controller may be configured to control activation of the controllable load circuitry to apply an event-based load to the power supply, for example, based on the current consumption event.

公开(公告)号：US11979177B2

公开(公告)日：2024-05-07

申请号：US17810845

申请日：2022-07-06

Applicant: Intel Corporation

Inventor： Elan Banin ,  Eytan Mann ,  Rotem Banin ,  Ronen Gernizky ,  Ofir Degani ,  Igal Kushnir ,  Shahar Porat ,  Amir Rubin ,  Vladimir Volokitin ,  Elinor Kashani ,  Dmitry Felsenstein ,  Ayal Eshkoli ,  Tal Davidson ,  Eng Hun Ooi ,  Yossi Tsfati ,  Ran Shimon

IPC: H04B1/04 ,  H04L7/033

CPC classification number: H04B1/04 ,  H04L7/0331

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

公开(公告)号：US11387852B2

公开(公告)日：2022-07-12

申请号：US16639780

申请日：2018-09-17

Applicant: Intel Corporation

Inventor： Elan Banin ,  Eytan Mann ,  Rotem Banin ,  Ronen Gernizky ,  Ofir Degani ,  Igal Kushnir ,  Shahar Porat ,  Amir Rubin ,  Vladimir Volokitin ,  Elinor Kashani ,  Dmitry Felsenstein ,  Ayal Eshkoli ,  Tai Davidson ,  Eng Hun Ooi ,  Yossi Tsfati ,  Ran Shimon

IPC: H04B1/04 ,  H04L7/033

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

公开(公告)号：US20200212943A1

公开(公告)日：2020-07-02

申请号：US16639780

申请日：2018-09-17

Applicant: Intel Corporation

Inventor： Elan Banin ,  Eytan Mann ,  Rotem Banin ,  Ronen Gernizky ,  Ofir Degani ,  Igal Kushnir ,  Shahar Porat ,  Amir Rubin ,  Vladimir Volokitin ,  Elinor Kashani ,  Dmitry Felsenstein ,  Ayal Eshkoli ,  Tal Davidson ,  Eng Hun Ooi ,  Yossi Tsfati ,  Ran Shimon

IPC: H04B1/04 ,  H04L7/033

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.