公开(公告)号：US12074618B2

公开(公告)日：2024-08-27

申请号：US17128787

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： James Guilford ,  Vinodh Gopal ,  Daniel Cutter

IPC: H03M7/42 ,  G06F9/46 ,  H03M7/30

CPC classification number: H03M7/42 ,  G06F9/461 ,  H03M7/3086

Abstract: An embodiment of an integrated circuit may comprise a hardware compressor to compress data, the hardware compressor including circuitry to store input data in a history buffer, compute one or more code tables based on the input data, and compute a compression stream header based on the computed one or more code tables. Other embodiments are disclosed and claimed.

公开(公告)号：US20200319959A1

公开(公告)日：2020-10-08

申请号：US16908686

申请日：2020-06-22

Applicant: INTEL CORPORATION

Inventor： Vinodh Gopal ,  James Guilford ,  Daniel Cutter ,  Kirk Yap

IPC: G06F11/10 ,  H03M7/30

Abstract: A processing device comprising compression circuitry to: determine a compression configuration to compress source data; generate a checksum of the source data in an uncompressed state; compress the source data into at least one block based on the compression configuration, wherein the at least one block comprises: a plurality of sub-blocks, wherein the plurality of sub-block includes a predetermined size; a block header corresponding to the plurality of sub-blocks; and decompression circuitry coupled to the compression circuitry, wherein the decompression circuitry to: while not outputting a decompressed data stream of the source data: generate index information corresponding to the plurality of sub-blocks; in response to generating the index information, generate a checksum of the compressed source data associated with the plurality of sub-blocks; and determine whether the checksum of the source data in the uncompressed format matches the checksum of the compressed source data.

公开(公告)号：US10691529B2

公开(公告)日：2020-06-23

申请号：US16013710

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James Guilford ,  Daniel Cutter ,  Kirk Yap

IPC: G06F11/10 ,  H03M7/30 ,  H03M7/40

Abstract: A processing device comprising compression circuitry to: determine a compression configuration to compress source data; generate a checksum of the source data in an uncompressed state; compress the source data into at least one block based on the compression configuration, wherein the at least one block comprises: a plurality of sub-blocks, wherein the plurality of sub-block includes a predetermined size; a block header corresponding to the plurality of sub-blocks; and decompression circuitry coupled to the compression circuitry, wherein the decompression circuitry to: while not outputting a decompressed data stream of the source data: generate index information corresponding to the plurality of sub-blocks; in response to generating the index information, generate a checksum of the compressed source data associated with the plurality of sub-blocks; and determine whether the checksum of the source data in the uncompressed format matches the checksum of the compressed source data.

公开(公告)号：US10270464B1

公开(公告)日：2019-04-23

申请号：US15941968

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： James Guilford ,  Kirk Yap ,  Vinodh Gopal ,  Daniel Cutter ,  Wajdi Feghali

IPC: H03M7/30 ,  H03M7/40

Abstract: An apparatus and method for performing efficient lossless compression. For example, one embodiment of an apparatus comprises: first compression circuitry to identify and replace one or more repeated bit strings from an input data stream with distances to the one or more repeated bit strings, the first compression circuitry to generate a first compressed data stream comprising literal-length data identifying a first instance of each repeated bit string and distance data comprising distances from the first instance to each repeated instance of the repeated bit string; second compression circuitry to perform sorting, tree generation, and length calculations for literal-length values and distance values of the first compressed data stream, the second compression circuitry comprising: variable length code mapping circuitry to map each literal-length value and distance value to a variable length code; header generation circuitry to generate a header for a final compressed bit stream using the length calculations; and a transcoder to substitute the variable length codes in place of the literal-length and distance values to generate a compressed bit stream body, wherein the transcoder operates in parallel with the header generation circuitry; and bit stream merge circuitry to combine the header with the compressed bit stream body to generate a final lossless compressed bitstream.

公开(公告)号：US11243836B2

公开(公告)日：2022-02-08

申请号：US16908686

申请日：2020-06-22

Applicant: INTEL CORPORATION

Inventor： Vinodh Gopal ,  James Guilford ,  Daniel Cutter ,  Kirk Yap

IPC: G06F11/10 ,  H03M7/30 ,  H03M7/40

Abstract: A processing device comprising compression circuitry to: determine a compression configuration to compress source data; generate a checksum of the source data in an uncompressed state; compress the source data into at least one block based on the compression configuration, wherein the at least one block comprises: a plurality of sub-blocks, wherein the plurality of sub-block includes a predetermined size; a block header corresponding to the plurality of sub-blocks; and decompression circuitry coupled to the compression circuitry, wherein the decompression circuitry to: while not outputting a decompressed data stream of the source data: generate index information corresponding to the plurality of sub-blocks; in response to generating the index information, generate a checksum of the compressed source data associated with the plurality of sub-blocks; and determine whether the checksum of the source data in the uncompressed format matches the checksum of the compressed source data.

公开(公告)号：US11095305B1

公开(公告)日：2021-08-17

申请号：US16391246

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： James Guilford ,  Kirk Yap ,  Vinodh Gopal ,  Daniel Cutter ,  Wajdi Feghali

IPC: H03M7/34 ,  H03M7/30 ,  H03M7/40

Abstract: An apparatus and method for performing efficient lossless compression. For example, one embodiment of an apparatus comprises: first compression circuitry to identify and replace one or more repeated bit strings from an input data stream with distances to the one or more repeated bit strings, the first compression circuitry to generate a first compressed data stream comprising literal-length data identifying a first instance of each repeated bit string and distance data comprising distances from the first instance to each repeated instance of the repeated bit string; second compression circuitry to perform sorting, tree generation, and length calculations for literal-length values and distance values of the first compressed data stream, the second compression circuitry comprising: variable length code mapping circuitry to map each literal-length value and distance value to a variable length code; header generation circuitry to generate a header for a final compressed bit stream using the length calculations; and a transcoder to substitute the variable length codes in place of the literal-length and distance values to generate a compressed bit stream body, wherein the transcoder operates in parallel with the header generation circuitry; and bit stream merge circuitry to combine the header with the compressed bit stream body to generate a final lossless compressed bitstream.

公开(公告)号：US20190034490A1

公开(公告)日：2019-01-31

申请号：US15856858

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Kirk Yap ,  James Guilford ,  Daniel Cutter ,  Vinodh Gopal

IPC: G06F17/30

Abstract: Technologies for determining set membership include a computing device that further includes one or more accelerator devices. Each accelerator device is to receive input data and definition table configuration data, the input data including a packed unsigned integers of column data from database and the definition table configuration data including a set membership query condition, generate a definition table indicative of element values that satisfy the set membership query condition, generate a lookup request for an element of the column data of the input data, perform the lookup request by accessing the definition table to determine whether the element satisfies the set membership query condition, and generate output indicative of whether the element is a member of the set membership.

公开(公告)号：US20220200626A1

公开(公告)日：2022-06-23

申请号：US17128787

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： James Guilford ,  Vinodh Gopal ,  Daniel Cutter

IPC: H03M7/42 ,  G06F9/46 ,  H03M7/30

Abstract: An embodiment of an integrated circuit may comprise a hardware compressor to compress data, the hardware compressor including circuitry to store input data in a history buffer, compute one or more code tables based on the input data, and compute a compression stream header based on the computed one or more code tables. Other embodiments are disclosed and claimed.

公开(公告)号：US20220100526A1

公开(公告)日：2022-03-31

申请号：US17033760

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： James Guilford ,  George Powley ,  Vinodh Gopal ,  Wajdi Feghali

IPC: G06F9/38

Abstract: Apparatus and method for performing low-latency multi-job submission via a single job descriptor is described herein. An apparatus embodiment includes a plurality of descriptor queues to stores job descriptors describing work to be performed and enqueue circuitry to receive a first job descriptor which includes a first field to store a Single Instruction Multiple Data (SIMD) width. If the SIMD width indicates that the first job descriptor is an SIMD job descriptor and open slots are available in the descriptor queues to store new job descriptors, then the enqueue circuitry is to generate a plurality of job descriptors based on fields of the first job descriptor and to store them in the open slots of the descriptor queues. The generated job descriptors are processed by processing pipelines to perform the work described. At least some of the generated job descriptors are processed concurrently or in parallel by different processing pipelines.

公开(公告)号：US11249761B2

公开(公告)日：2022-02-15

申请号：US16934003

申请日：2020-07-20

Applicant: Intel Corporation

Inventor： Dan Baum ,  Michael Espig ,  James Guilford ,  Wajdi K. Feghali ,  Raanan Sade ,  Christopher J. Hughes ,  Robert Valentine ,  Bret Toll ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney ,  Vinodh Gopal ,  Ronen Zohar ,  Alexander F. Heinecke

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.