公开(公告)号：US10924591B2

公开(公告)日：2021-02-16

申请号：US16014690

申请日：2018-06-21

Applicant: INTEL CORPORATION

Inventor： Wajdi Feghali ,  Vinodh Gopal ,  Kirk Yap ,  Sean Gulley ,  Simon Peffers

IPC: H04L29/06 ,  H04L12/863

Abstract: Methods and apparatus for low-latency link compression schemes. Under the schemes, selected packets or messages are dynamically selected for compression in view of current transmit queue levels. The latency incurred during compression and decompression is not added to the data-path, but sits on the side of the transmit queue. The system monitors the queue depth and, accordingly, initiates compression jobs based on the depth. Different compression levels may be dynamically selected and used based on queue depth. Under various schemes, either packets or messages are enqueued in the transmit queue or pointers to such packets and messages are enqueued. Additionally, packets/message may be compressed prior to being enqueued, or after being enqueued, wherein an original uncompressed packet is replaced with a compressed packet. Compressed and uncompressed packets may be stored in queues or buffers and transmitted using a different numbers of transmit cycles based on their compression ratios. The schemes may be implemented to improve the effective bandwidth of various types of links, including serial links, bus-type links, and socket-to-socket links in multi-socket systems.

公开(公告)号：US20190188132A1

公开(公告)日：2019-06-20

申请号：US15845271

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Kirk Yap ,  James D. Guilford ,  Simon N. Peffers ,  Vinodh Gopal

IPC: G06F12/084 ,  G06F17/30 ,  G06F13/16 ,  G06F3/06

CPC classification number: G06F12/084 ,  G06F3/0629 ,  G06F13/1652 ,  G06F13/1668 ,  G06F16/2453 ,  G06F2212/621

Abstract: Various systems and methods for hardware acceleration circuitry are described. In an embodiment, circuitry is to perform 1-bit comparisons of elements of variable M-bit width aligned to N-bit width, where N is a power of 2, in a data path of P-bit width. Second and subsequent scan stages use the comparison results from the previous stage to perform 1-bit comparison of adjacent results, so that each subsequent stage results in a full comparison of element widths double that of the previous stage. A total number of stages required to scan, or filter, M-bit elements in N-bit width lanes is equal 1+log 2(N), and the total number of stages required for implementation in the circuitry is 1+log 2(P), where P is the maximum width of the data path comprising 1 to P elements.

公开(公告)号：US09503256B2

公开(公告)日：2016-11-22

申请号：US14582707

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Kirk Yap ,  Gilbert Wolrich ,  Sudhir Satpathy ,  Sean Gulley ,  Vinodh Gopal ,  Sanu Mathew ,  Wajdi Feghali

IPC: H04L9/00 ,  H04L9/08 ,  H04L9/14

CPC classification number: H04L9/0822 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/122

Abstract: Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.

Abstract translation: 公开了用于SMS4加速硬件的发明的实施例。 在一个实施例中，一种装置包括SMS4硬件和密钥变换硬件。 SMS4硬件是执行一轮加密和一轮密钥扩展。 密钥转换硬件是转换密钥以提供SMS4硬件来执行一轮解密。

公开(公告)号：US20190391869A1

公开(公告)日：2019-12-26

申请号：US16013710

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James Guilford ,  Daniel Cutter ,  Kirk Yap

IPC: G06F11/10 ,  H03M7/30

Abstract: A processing device comprising compression circuitry to: determine a compression configuration to compress source data; generate a checksum of the source data in an uncompressed state; compress the source data into at least one block based on the compression configuration, wherein the at least one block comprises: a plurality of sub-blocks, wherein the plurality of sub-block includes a predetermined size; a block header corresponding to the plurality of sub-blocks; and decompression circuitry coupled to the compression circuitry, wherein the decompression circuitry to: while not outputting a decompressed data stream of the source data: generate index information corresponding to the plurality of sub-blocks; in response to generating the index information, generate a checksum of the compressed source data associated with the plurality of sub-blocks; and determine whether the checksum of the source data in the uncompressed format matches the checksum of the compressed source data.

公开(公告)号：US20190042611A1

公开(公告)日：2019-02-07

申请号：US15868594

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Kirk Yap ,  James Guilford ,  Daniel Cutter ,  Vinodh Gopal

IPC: G06F17/30

Abstract: Technologies for determining unique values include a computing device that further includes one or more accelerator devices. Each accelerator device is to receive input data and query configuration data, the input data including a packed array of unsigned integers of column data from a database and the query configuration data including an element width of the input data, and generate, in response to receiving the query configuration data, a bit-map output table based on the query configuration data, generate a write request for each element of the input data to set a corresponding bit-map output bit of the bit-map output table which corresponds to an element value of the corresponding element. Subsequently, the accelerator device is further to set the corresponding bit-map output bit to indicate a presence of the corresponding element and output the bit-map output table indicative of unique elements that are present in the input data.

公开(公告)号：US09047082B2

公开(公告)日：2015-06-02

申请号：US14254233

申请日：2014-04-16

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  Shay Gueron ,  Gilbert Wolrich ,  Wajdi Feghali ,  Kirk Yap ,  Bradley Burres

IPC: G06F11/00 ,  G06F9/30 ,  H03M13/09 ,  G06F11/10

CPC classification number: G06F9/30145 ,  G06F9/30018 ,  G06F11/1004 ,  H03M13/09 ,  H03M13/091

Abstract: A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.

Abstract translation: 提供了使用多个不同的n位多项式对数据块执行循环冗余校验（CRC）操作的方法和装置。 灵活的CRC指令使用可编程的n位多项式来执行CRC操作。 通过将n位多项式存储在两个操作数之一中，将n位多项式提供给CRC指令。

公开(公告)号：US11243836B2

公开(公告)日：2022-02-08

申请号：US16908686

申请日：2020-06-22

Applicant: INTEL CORPORATION

Inventor： Vinodh Gopal ,  James Guilford ,  Daniel Cutter ,  Kirk Yap

IPC: G06F11/10 ,  H03M7/30 ,  H03M7/40

Abstract: A processing device comprising compression circuitry to: determine a compression configuration to compress source data; generate a checksum of the source data in an uncompressed state; compress the source data into at least one block based on the compression configuration, wherein the at least one block comprises: a plurality of sub-blocks, wherein the plurality of sub-block includes a predetermined size; a block header corresponding to the plurality of sub-blocks; and decompression circuitry coupled to the compression circuitry, wherein the decompression circuitry to: while not outputting a decompressed data stream of the source data: generate index information corresponding to the plurality of sub-blocks; in response to generating the index information, generate a checksum of the compressed source data associated with the plurality of sub-blocks; and determine whether the checksum of the source data in the uncompressed format matches the checksum of the compressed source data.

公开(公告)号：US11108406B2

公开(公告)日：2021-08-31

申请号：US16445556

申请日：2019-06-19

Applicant: Intel Corporation

Inventor： Simon N. Peffers ,  Vinodh Gopal ,  Kirk Yap

IPC: H03M7/38 ,  H03M7/30 ,  G06F12/0875 ,  G06F12/0888 ,  G06F9/54

Abstract: In one embodiment, an apparatus includes: a compression circuit to compress data blocks of one or more traffic classes; and a control circuit coupled to the compression circuit, where the control circuit is to enable the compression circuit to concurrently compress data blocks of a first traffic class and not to compress data blocks of a second traffic class. Other embodiments are described and claimed.

公开(公告)号：US11095305B1

公开(公告)日：2021-08-17

申请号：US16391246

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： James Guilford ,  Kirk Yap ,  Vinodh Gopal ,  Daniel Cutter ,  Wajdi Feghali

IPC: H03M7/34 ,  H03M7/30 ,  H03M7/40

Abstract: An apparatus and method for performing efficient lossless compression. For example, one embodiment of an apparatus comprises: first compression circuitry to identify and replace one or more repeated bit strings from an input data stream with distances to the one or more repeated bit strings, the first compression circuitry to generate a first compressed data stream comprising literal-length data identifying a first instance of each repeated bit string and distance data comprising distances from the first instance to each repeated instance of the repeated bit string; second compression circuitry to perform sorting, tree generation, and length calculations for literal-length values and distance values of the first compressed data stream, the second compression circuitry comprising: variable length code mapping circuitry to map each literal-length value and distance value to a variable length code; header generation circuitry to generate a header for a final compressed bit stream using the length calculations; and a transcoder to substitute the variable length codes in place of the literal-length and distance values to generate a compressed bit stream body, wherein the transcoder operates in parallel with the header generation circuitry; and bit stream merge circuitry to combine the header with the compressed bit stream body to generate a final lossless compressed bitstream.

公开(公告)号：US20190042481A1

公开(公告)日：2019-02-07

申请号：US16145659

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Wajdi Feghali ,  Vinodh Gopal ,  Kirk Yap ,  Sean Gulley ,  Raghunandan Makaram

IPC: G06F12/14 ,  G06F12/1027 ,  G06F12/02 ,  H04L9/08

Abstract: Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.