公开(公告)号：US10230665B2

公开(公告)日：2019-03-12

申请号：US14136293

申请日：2013-12-20

Applicant: INTEL CORPORATION

Inventor： Thomas D. Lovett ,  Albert Cheng ,  Mark S. Birrittella ,  James Kunz ,  Todd Rimmer

IPC: H04L12/933 ,  H04L12/911 ,  H04L1/00 ,  H04L12/851 ,  H04L12/805 ,  H04L12/863 ,  H04L12/865 ,  H04L1/12 ,  H04L25/14

Abstract: Methods, apparatus, and systems for implementing hierarchical and lossless packet preemption and interleaving to reduce latency jitter in flow-controller packet-based networks. Fabric packets are divided into a plurality of data units, with data units for different fabric packets buffered in separate buffers. Data units are pulled from the buffers and added to a transmit stream in which groups of data units are interleaved. Upon receipt by a receiver, the groups of data units are separated out and buffered in separate buffers under which data units for the same fabric packets are grouped together. In one aspect, each buffer is associated with a respective virtual lane (VL), and the fabric packets are effectively transferred over fabric links using virtual lanes. VLs may have different levels of priority under which data units for fabric packets in higher-priority VLs may preempt fabric packets in lower-priority VLs. By transferring data units rather than entire packets, transmission of a packet can be temporarily paused in favor of a higher-priority packet. Multiple levels of preemption and interleaving in a nested manner are supported.

公开(公告)号：US10015056B2

公开(公告)日：2018-07-03

申请号：US15207706

申请日：2016-07-12

Applicant: Intel Corporation

Inventor： Michael Heinz ,  Todd Rimmer ,  James Kunz ,  Mark Debbage

IPC: H04L12/28 ,  H04L12/24 ,  H04L12/753 ,  H04L12/751 ,  G06F9/50

CPC classification number: H04L41/12 ,  G06F9/5066 ,  H04L41/0213 ,  H04L41/046 ,  H04L41/0893 ,  H04L45/08 ,  H04L45/48

Abstract: System, method, and apparatus for improving the performance of collective operations in High Performance Computing (HPC). Compute nodes in a networked HPC environment form collective groups to perform collective operations. A spanning tree is formed including the compute nodes and switches and links used to interconnect the compute nodes, wherein the spanning tree is configured such that there is only a single route between any pair of nodes in the tree. The compute nodes implement processes for performing the collective operations, which includes exchanging messages between processes executing on other compute nodes, wherein the messages contain indicia identifying collective operations they belong to. Each switch is configured to implement message forwarding operations for its portion of the spanning tree. Each of the nodes in the spanning tree implements a ratcheted cyclical state machine that is used for synchronizing collective operations, along with status messages that are exchanged between nodes. Transaction IDs are also used to detect out-of-order and lost messages.