公开(公告)号：US09971685B2

公开(公告)日：2018-05-15

申请号：US15089133

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Jason A. Gayman ,  Robert W. Faber

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/00

CPC classification number: G06F12/0646 ,  G06F2212/7211

Abstract: A first set representing a first plurality of physical block addresses of a non-volatile memory and a second set representing a second plurality of physical block addresses of the non-volatile memory may be identified. In response to a request to perform a wear leveling operation, first data from a first physical block address of the first set may be swapped with second data from a first physical block address of the second set. A second physical block address of the first set that is adjacent to the first physical block address of the first set may be identified. Third data from the second physical block address of the first set may be swapped with fourth data from a second physical block address of the second set that is adjacent to the first physical block of the second set.

公开(公告)号：US20170286293A1

公开(公告)日：2017-10-05

申请号：US15089133

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Jason A. Gayman ,  Robert W. Faber

IPC: G06F12/06

CPC classification number: G06F12/0646 ,  G06F2212/7211

Abstract: A first set representing a first plurality of physical block addresses of a non-volatile memory and a second set representing a second plurality of physical block addresses of the non-volatile memory may be identified. In response to a request to perform a wear leveling operation, first data from a first physical block address of the first set may be swapped with second data from a first physical block address of the second set. A second physical block address of the first set that is adjacent to the first physical block address of the first set may be identified. Third data from the second physical block address of the first set may be swapped with fourth data from a second physical block address of the second set that is adjacent to the first physical block of the second set.

公开(公告)号：US10452312B2

公开(公告)日：2019-10-22

申请号：US15396204

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Zhe Wang ,  Zeshan A. Chishti ,  Muthukumar P. Swaminathan ,  Alaa R. Alameldeen ,  Kunal A. Khochare ,  Jason A. Gayman

IPC: G06F3/06 ,  G11C16/34 ,  G11C16/26

Abstract: Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively. A second voltage level is used to read data from read addresses that do not map to one of the first and the second level indications the first and second level data structures, respectively.