公开(公告)号：US10310989B2

公开(公告)日：2019-06-04

申请号：US15721379

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Philip Hillier ,  Jeffrey W. Ryden ,  Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Kunal A. Khochare ,  Richard P. Mangold ,  Prashant S. Damle

IPC: G06F12/126 ,  G06F12/02 ,  G11C7/22

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.

公开(公告)号：US20190042445A1

公开(公告)日：2019-02-07

申请号：US15670320

申请日：2017-08-07

Applicant: Intel Corporation

Inventor： Muthukumar P. Swaminathan ,  Murugasamy K. Nachimuthu ,  Mahesh S. Natu

IPC: G06F12/0873 ,  G06F12/0868

Abstract: Technologies for caching persistent two-level memory (2LM) data include a memory and a processor. The memory includes a volatile memory device and a non-volatile memory device. The processor determines a persistent memory address space for persistent 2LM data and determines one or more non-volatile memory devices that the persistent memory address space is mapped to. The processor further configures the persistent memory address space of the non-volatile memory device to operate in a persistent 2LM mode and further configures an operating system to cache accesses to persistent memory address space in volatile memory.

公开(公告)号：US10719443B2

公开(公告)日：2020-07-21

申请号：US16363992

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

IPC: G11C11/406 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G11C14/00

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US10459659B2

公开(公告)日：2019-10-29

申请号：US15475341

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Muthukumar P. Swaminathan ,  Kunal A. Khochare

IPC: G06F3/06 ,  G06F13/16 ,  G11C8/12 ,  G11C16/08 ,  G11C16/20

Abstract: Technologies for issuing commands on selected memory devices includes an apparatus that includes a data storage controller and multiple non-volatile, write in place, byte or block addressable memory devices. The memory devices are arranged in one or more ranks, and the memory devices in each rank are connected to a same communication channel. The data storage controller is to select a subgroup of the plurality of the memory devices in a rank without modifying an identifier of each memory device, and issue a command to operate on data of the selected subgroup.

公开(公告)号：US11074188B2

公开(公告)日：2021-07-27

申请号：US16278509

申请日：2019-02-18

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Alaa R. Alameldeen ,  Lidia Warnes ,  Andy M. Rudoff ,  Muthukumar P. Swaminathan

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/02 ,  G06F12/0893

Abstract: A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.

公开(公告)号：US10691626B2

公开(公告)日：2020-06-23

申请号：US16405524

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Bill Nale ,  Raj K. Ramanujan ,  Muthukumar P. Swaminathan ,  Tessil Thomas ,  Taarinya Polepeddi

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0804 ,  G06F9/46 ,  G06F12/0868 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0897 ,  G06F12/0811

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

公开(公告)号：US10678315B2

公开(公告)日：2020-06-09

申请号：US16147950

申请日：2018-10-01

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Muthukumar P. Swaminathan ,  Doyle Rivers

IPC: G06F1/20 ,  G06F1/3234 ,  G06F1/3225

Abstract: Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may monitor the temperature of the memory resource in real-time. A comparator in the memory resource may indicate a high temperature condition to a memory controller. The memory controller, in response to the high temperature condition, can restrict or halt data flow to the memory resource. When the real-time temperature of the memory resource falls below a defined threshold, the memory controller may resume data flow to the memory resource.

公开(公告)号：US10241943B2

公开(公告)日：2019-03-26

申请号：US15857992

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Bill Nale ,  Raj K. Ramanujan ,  Muthukumar P. Swaminathan ,  Tessil Thomas ,  Taarinya Polepeddi

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/0868 ,  G06F11/10 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0897 ,  G06F9/46 ,  G06F13/40 ,  G06F12/02 ,  G06F12/0811

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol

公开(公告)号：US10073659B2

公开(公告)日：2018-09-11

申请号：US14751846

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： James Alexander ,  Muthukumar P. Swaminathan ,  Richard P. Mangold

IPC: G06F1/26 ,  G06F1/32 ,  G06F3/06 ,  G06F9/50

CPC classification number: G06F3/0673 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/329 ,  G06F3/0625 ,  G06F3/0653 ,  G06F9/5094 ,  Y02D10/152 ,  Y02D10/24

Abstract: A method is described. The method includes receiving an indication of an activity of load circuitry of a power supply. The method includes, in response to the indication, generating a first signal that describes the activity and a second signal that describes whether the event is initiating or completing. The method includes determining a weight amount from the first signal and adjusting a credit count by the weight amount up or down based on the second signal. The method includes comparing the credit count against a first threshold. The method includes calculating an average credit count that accounts for the credit count and previous credit counts and comparing the average credit count against a second threshold. The method includes adjusting an activity level of the load circuitry if either threshold is crossed.

公开(公告)号：US10282323B2

公开(公告)日：2019-05-07

申请号：US16046587

申请日：2018-07-26

Applicant: Intel Corporation

Inventor： Bill Nale ,  Raj K. Ramanujan ,  Muthukumar P. Swaminathan ,  Tessil Thomas ,  Taarinya Polepeddi

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/02 ,  G06F12/0897 ,  G06F13/40 ,  G06F9/46 ,  G06F12/0804 ,  G06F11/10 ,  G06F12/0868 ,  G06F12/0802 ,  G06F13/00 ,  G06F12/0811

Abstract: A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.