公开(公告)号：US10310989B2

公开(公告)日：2019-06-04

申请号：US15721379

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Philip Hillier ,  Jeffrey W. Ryden ,  Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Kunal A. Khochare ,  Richard P. Mangold ,  Prashant S. Damle

IPC: G06F12/126 ,  G06F12/02 ,  G11C7/22

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.

公开(公告)号：US20190258414A1

公开(公告)日：2019-08-22

申请号：US16405296

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Kunal A. Khochare ,  Camille C. Raad ,  Richard P. Mangold ,  Shachi K. Thakkar

IPC: G06F3/06 ,  G06F12/02

Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.

公开(公告)号：US20190102320A1

公开(公告)日：2019-04-04

申请号：US15721379

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Philip Hillier ,  Jeffrey W. Ryden ,  Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Kunal A. Khochare ,  Richard P. Mangold ,  Prashant S. Damle

IPC: G06F12/126 ,  G06F12/02 ,  G11C7/22

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.

公开(公告)号：US10459659B2

公开(公告)日：2019-10-29

申请号：US15475341

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Muthukumar P. Swaminathan ,  Kunal A. Khochare

IPC: G06F3/06 ,  G06F13/16 ,  G11C8/12 ,  G11C16/08 ,  G11C16/20

Abstract: Technologies for issuing commands on selected memory devices includes an apparatus that includes a data storage controller and multiple non-volatile, write in place, byte or block addressable memory devices. The memory devices are arranged in one or more ranks, and the memory devices in each rank are connected to a same communication channel. The data storage controller is to select a subgroup of the plurality of the memory devices in a rank without modifying an identifier of each memory device, and issue a command to operate on data of the selected subgroup.

公开(公告)号：US10915254B2

公开(公告)日：2021-02-09

申请号：US16405296

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Kunal A. Khochare ,  Camille C. Raad ,  Richard P. Mangold ,  Shachi K. Thakkar

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0866 ,  G06F11/16 ,  G06F11/00 ,  G06F12/0888

Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.

公开(公告)号：US10452312B2

公开(公告)日：2019-10-22

申请号：US15396204

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Zhe Wang ,  Zeshan A. Chishti ,  Muthukumar P. Swaminathan ,  Alaa R. Alameldeen ,  Kunal A. Khochare ,  Jason A. Gayman

IPC: G06F3/06 ,  G11C16/34 ,  G11C16/26

Abstract: Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively. A second voltage level is used to read data from read addresses that do not map to one of the first and the second level indications the first and second level data structures, respectively.

公开(公告)号：US10296238B2

公开(公告)日：2019-05-21

申请号：US14975160

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Kunal A. Khochare ,  Camille C. Raad ,  Richard P. Mangold ,  Shachi K. Thakkar

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.

公开(公告)号：US20180285020A1

公开(公告)日：2018-10-04

申请号：US15475341

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Muthukumar P. Swaminathan ,  Kunal A. Khochare

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0688 ,  G06F13/1668 ,  G11C8/12 ,  G11C16/08 ,  G11C16/20

Abstract: Technologies for issuing commands on selected memory devices includes an apparatus that includes a data storage controller and multiple non-volatile, write in place, byte or block addressable memory devices. The memory devices are arranged in one or more ranks, and the memory devices in each rank are connected to a same communication channel. The data storage controller is to select a subgroup of the plurality of the memory devices in a rank without modifying an identifier of each memory device, and issue a command to operate on data of the selected subgroup.

公开(公告)号：US09934859B1

公开(公告)日：2018-04-03

申请号：US15391763

申请日：2016-12-27

Applicant: INTEL CORPORATION

Inventor： Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Prashant S. Damle ,  Kunal A. Khochare ,  Philip Hillier ,  Jeffrey W. Ryden ,  Richard P. Mangold

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028

Abstract: In response to a write operation on a storage element in a non-volatile memory device, a count provided by a global counter is stored to indicate a time at which the write operation occurs on the storage element. In response to receiving a request perform a read operation on the storage element, a determination is made of a demarcation voltage to apply for performing the read operation on the storage element, based on a progress of the global counter since the write operation on the storage element.